Method for making a semiconductor device that includes a metal gate electrode

• US 7,160,767 B2
• Filed: 12/18/2003
• Issued: 01/09/2007
• Est. Priority Date: 12/18/2003
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Shah, Uday, Chau, Robert S., Doczy, Mark L., Kavalieros, Jack, Brask, Justin K., Metz, Matthew V.
• Primary Examiner(s): Deo; Duy-Vu N
• Application Number:
  US10/739,173
• Publication Number:
  US 20050136677A1
• Time in Patent Office: 1,118 Days
• Field of Search: 438396-399, 438299-303, 438/197, 438/585, 438/586
• US Class Current: 438/195
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/0338 Process specially adapted to improve the resolution of the mask
• CPC Class Codes: H01L 21/28079 the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/511 with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Abstract

A method for making a semiconductor device is described. That method comprises forming a dummy dielectric layer that is at least about 10 angstroms thick on a substrate, and forming a sacrificial layer on the dummy dielectric layer. After removing the sacrificial layer and the dummy dielectric layer to generate a trench that is positioned between first and second spacers, a gate dielectric layer is formed on the substrate at the bottom of the trench, and a metal layer is formed on the gate dielectric layer.

Claims

1. A method for making a semiconductor device comprising:

forming on a substrate a nitrided silicon dioxide layer that is between about 10 and about 30 angstroms thick;

forming on the nitrided silicon dioxide layer a polysilicon containing layer that is between about 100 and about 2,000 angstroms thick;

forming a first silicon nitride layer that is between about 100 and about 500 angstroms thick on the polysilicon containing layer;

forming an etch stop layer that is between about 200 and about 1,200 angstroms thick on the first silicon nitride layer;

etching the etch stop layer, the first silicon nitride layer, the polysilicon containing layer, and the nitrided silicon dioxide layer, to form a patterned etch stop layer, a patterned first silicon nitride layer, a patterned polysilicon containing layer, and a patterned nitrided silicon dioxide layer;

depositing a second silicon nitride layer on the substrate, the patterned etch stop layer and on opposite sides of the patterned polysilicon containing layer;

removing the second silicon nitride layer from part of the substrate and from the patterned etch stop layer to form first and second spacers on opposite sides of the patterned polysilicon containing layer;

forming a dielectric layer on the patterned etch stop layer and on the substrate;

removing the dielectric layer from the patterned etch stop layer;

removing the patterned etch stop layer and the patterned first silicon nitride layer;

removing the patterned polysilicon containing layer and the patterned nitrided silicon dioxide layer to generate the trench that is positioned between the first and second spacers;

forming a high-k gate dielectric layer on the substrate at the bottom of the trench; and

filling at least part of the trench with a metal layer that is formed on the high-k gate dielectric layer.

2. The method of claim 1 wherein the nitrided silicon dioxide layer is at least about 15 angstroms thick.

3. The method of claim 2 wherein:

the etch stop layer comprises a material that is selected from the group consisting of silicon dioxide, silicon carbide, a metal carbide, a carbon doped silicon oxide, a carbon doped silicon nitride, and a metal oxide;

the high-k gate dielectric layer is formed by atomic layer chemical vapor deposition and comprises a material that is selected from the group consisting of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate; and

the metal layer fills the entire trench and comprises a material that is selected from the group consisting of hafnium, zirconium, titanium, tantalum, aluminum, a metal carbide, ruthenium, palladium, platinum, cobalt, nickel, and a conductive metal oxide.

4. The method of claim 2 wherein the metal layer comprises a material that is selected from the group consisting of hafnium, zirconium, titanium, tantalum, aluminum, and a metal carbide, and has a workfunction that is between about 3.9 eV and about 4.2 eV.

5. The method of claim 2 wherein the metal layer comprises a material that is selected from the group consisting of ruthenium, palladium, platinum, cobalt, nickel, and a conductive metal oxide, and has a workfunction that is between about 4.9 eV and about 5.2 eV.

6. The method of claim 2 wherein:

a chemical mechanical polishing process is used to remove the dielectric layer from the patterned etch stop layer, and to remove the patterned etch stop layer and the patterned first silicon nitride layer; and

the metal layer serves as a workfunction metal that fills only part of the trench and is between about 50 and about 1,000 angstroms thick; and

further comprising depositing on the metal layer a trench fill metal that is selected from the group consisting of tungsten, aluminum, titanium, and titanium nitride.

7. A method for making a semiconductor device comprising:

forming on a substrate a dummy dielectric layer;

forming a sacrificial layer on the dummy dielectric layer;

forming a first silicon nitride layer on the sacrificial layer;

forming an etch stop layer on the first silicon nitride layer;

patterning the etch stop layer, the first silicon nitride layer, the sacrificial layer, and the dummy dielectric layer;

forming first and second spacers on opposite sides of the patterned sacrificial layer;

removing the patterned etch stop layer, the patterned first silicon nitride layer, the patterned sacrificial layer, and the patterned dummy dielectric layer to generate a trench that is positioned between the first and second spacers;

forming a gate dielectric layer on the substrate at the bottom of the trench; and

forming a metal layer on the gate dielectric layer.

8. The method of claim 7, wherein the forming of the first and second spacers comprises:

depositing a second silicon nitride layer on the substrate, on the patterned etch stop layer, and on opposite sides of the patterned sacrificial layer; and

removing the second silicon nitride layer from part of the substrate and from the patterned etch stop layer to form the first and second spacers on opposite sides of the patterned sacrificial layer.

9. The method of claim 7, further comprising forming source and drain regions that comprise a silicide next to the first and second spacers.

10. The method of claim 7, further comprising:

forming a second dielectric layer on the patterned etch stop layer and on the substrate; and

removing the second dielectric layer from the patterned etch stop layer.

11. The method of claim 7, wherein the dummy dielectric layer comprises a nitrided silicon dioxide that is at least about 10 angstroms thick.

12. The method of claim 7, wherein:

the gate dielectric layer comprises a material that is selected from the group consisting of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate; and

the metal layer comprises a material that is selected from the group consisting of hafnium, zirconium, ruthenium, palladium, cobalt, nickel, and a metal carbide.

13. A method for making a semiconductor device comprising:

forming a silicon dioxide layer on a substrate;

forming a polysilicon containing layer that is between about 100 and about 2,000 angstroms thick on the silicon dioxide layer;

forming a hard mask layer that is between about 100 and about 500 angstroms thick on the polysilicon containing layer;

forming an etch stop layer that is between about 200 and about 1,200 angstroms thick on the hard mask layer;

etching the etch stop layer, the hard mask layer, the polysilicon containing layer, and the silicon dioxide layer to form a patterned etch stop layer, a patterned hard mask layer, a patterned polysilicon containing layer, and a patterned silicon dioxide layer;

depositing a silicon nitride layer on the substrate, the patterned etch stop layer, and on opposite sides of the patterned polysilicon containing layer;

removing the silicon nitride layer from part of the substrate and from the patterned etch stop layer to form first and second spacers on opposite sides of the patterned polysilicon containing layer;

removing the patterned etch stop layer, the patterned hard mask layer, the patterned polysilicon containing layer, and the patterned silicon dioxide layer to generate a trench that is positioned between the first and second spacers;

forming a high-k gate dielectric layer on the substrate at the bottom of the trench; and

filling at least part of the trench with a metal layer that comprises a metal carbide and that is formed on the high-k gate dielectric layer.

14. The method of claim 13, further comprising:

forming a dielectric layer on the patterned etch stop layer and on the substrate; and

removing the dielectric layer from the patterned etch stop layer.

15. The method of claim 13, wherein:

the high-k gate dielectric layer comprises a material that is selected from the group consisting of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate; and

the metal layer fills the entire trench and comprises a material that is selected from the group consisting of hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide.