Edge termination in MOS transistors

• US 7,160,793 B2
• Filed: 02/25/2005
• Issued: 01/09/2007
• Est. Priority Date: 09/13/2001
• Status: Expired due to Fees

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Hijzen, Erwin A., Hueting, Raymond J. E., In't Zandt, Michael A. A.
• Primary Examiner(s): Weiss; Howard
• Assistant Examiner(s): INGHAM, JOHN C
• Application Number:
  US11/066,408
• Publication Number:
  US 20050156232A1
• Time in Patent Office: 683 Days
• Field of Search: 438/271, 438/588, 438/589, 257/332
• US Class Current: 438/588
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A RESURF trench gate MOSFET has a sufficiently small pitch (close spacing of neighbouring trenches) that intermediate areas of the drain drift region are depleted in the blocking condition of the MOSFET. However, premature breakdown can still occur in this known device structure at the perimeter/edge of the active device area and/or adjacent the gate bondpad. To counter premature breakdown, the invention adopts two principles:

• • the gate bondpad is either connected to an underlying stripe trench network surrounded by active cells, or is directly on top of the active cells, and
  • a compatible 2D edge termination scheme is provided around the RESURF active device area.

These principles can be implemented in various cellular layouts e.g. a concentric annular device geometry, which may be circular or rectangular or ellipsoidal, in the active area and in the edge termination, or a device array of such concentric hexagonal or circular stripe cells, or a device array of square active cells with stripe edge cells, or a device array of hexagonal active cells with an edge termination of hexagonal edge cells.

Claims

1. A method of manufacturing a semiconductor device comprises:

forming in a semiconductor body an active cell area wherein trenches containing gate material extend into the semiconductor body from a surface thereof, and forming;

adjacent to each trench gate;

a source region in the active cell area at said semiconductor body surface;

forming in the semiconductor body an inactive cell area wherein trenches containing gate material extend into the semiconductor body from the surface thereof, said source region not being formed in the inactive cell area; and

;

forming a gate bondpad over the active cell area and connected thereto;

said gate bondpad not extending beyond the active cell area.

2. A method according to claim 1, in which the source region is implanted prior to formation of said trenches.

3. A method as claimed in claim 1, in which the subsidiary inactive area comprises a stripe trench network of inactive cells.