Low threshold voltage PMOS apparatus and method of fabricating the same

• US 7,161,213 B2
• Filed: 08/05/2004
• Issued: 01/09/2007
• Est. Priority Date: 08/05/2004
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Ito, Akira, Chen, Henry K.
• Primary Examiner(s): Lee; Calvin
• Application Number:
  US10/911,720
• Publication Number:
  US 20060030092A1
• Time in Patent Office: 887 Days
• Field of Search: 438/156, 438/173, 438227-228, 257/276, 257/289, 257/327, 257/349, 257/362, 257/376
• US Class Current: 257/349
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823892 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A P-type metal oxide semiconductor (PMOS) device can include an N-well that does not extend completely throughout the active region of the PMOS device. For example, the PMOS device can be fabricated using a masking step to provide an N-well having an inner perimeter and an outer perimeter. The inner perimeter of the N-well surrounds at least a portion of the active region of the PMOS device. According to an embodiment, the inner perimeter of the N-well surrounds the entire active region. The PMOS device can include a deep N-well in contact with the N-well.

Claims

1. A P-type metal oxide semiconductor (PMOS) device, comprising:

an active region;

a first P+ region implanted into a p-type semiconductor substrate coupled to the active region forming a drain;

a second P+ region implanted into the p-type semiconductor substrate coupled to the active region forming a source; and

an N-well having an inner perimeter and an outer perimeter, wherein the inner perimeter surrounds at least a portion of the active region; and

a halo implant region in contact with a the source and a the drain of the PMOS device, the halo implant region more heavily doped than said N-well.

2. The PMOS device of claim 1, having a threshold voltage of approximately zero volts.

3. The PMOS device of claim 1, having a positive threshold voltage.

4. The PMOS device of claim 1, wherein the halo implant region includes a first halo implant region in contact with the source and a second halo implant region in contact with the drain, and the first halo implant region is in contact with the second halo implant region.

5. The PMOS device of claim 1, wherein the halo implant region hinders punchthrough.

6. The PMOS device of claim 1, further comprising:

a gate that defines a channel having a channel length; and

a P-LDD region that reduces an impact of the channel length on a threshold voltage of the PMOS device.

7. The PMOS device of claim 1, wherein the inner perimeter completely laterally surrounds the active region.

8. The PMOS device of claim 1, further comprising a deep N-well in contact with the N-well.

9. A P-type metal oxide semiconductor (PMOS) device, comprising:

an active region;

an N-well having an inner perimeter and an outer perimeter, wherein the inner perimeter surrounds at least a portion of the active region; and

a halo implant region in contact with a source and a drain including a first halo implant region in contact with the source and a second halo implant region in contact with the drain, and the first halo implant region is in contact with the second halo implant region, the halo implant region more heavily doped than the N-well.

10. The PMOS device of claim 9, wherein the halo implant region hinders punchthrough.

11. The PMOS device of claim 9, further comprising:

a gate that defines a channel having a channel length; and

a P-LDD region that reduces an impact of the channel length on a threshold voltage of the metal oxide semiconductor device.

12. The PMOS device of claim 9, wherein the inner perimeter completely laterally surrounds the active region.

13. The PMOS device of claim 9, further comprising a deep N-well in contact with the N-well.