Method for testing using a universal wafer carrier for wafer level die burn-in

• US 7,161,373 B2
• Filed: 06/30/2005
• Issued: 01/09/2007
• Est. Priority Date: 08/29/1990
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Wood, Alan G., Corbett, Tim J.
• Primary Examiner(s): KARLSEN, ERNEST F
• Application Number:
  US11/172,326
• Publication Number:
  US 20050253619A1
• Time in Patent Office: 558 Days
• Field of Search: None
• US Class Current: 324/754.13
• CPC Class Codes: G01R 1/0466 concerning contact pieces or mechanical details, e.g. hinges or cams; Shielding
• CPC Class Codes: G01R 1/0483 Sockets for un-leaded IC's having matrix type contact fields, e.g. BGA or PGA devices; Sockets for unpackaged, naked chips for IC's with connecting points around the edges only G01R1/0433
• CPC Class Codes: G01R 1/0491 for testing integrated circuits on wafers, e.g. wafer-level test cartridge
• CPC Class Codes: G01R 1/0735 arranged on a flexible frame or film
• CPC Class Codes: G01R 3/00 Apparatus or processes specially adapted for the manufacture or maintenance of measuring instruments , e.g. of probe tips
• CPC Class Codes: G01R 31/28 Testing of electronic circuits, e.g. by signal tracer EMC, EMP or similar testing of electronic circuits G01R31/002; testing for short-circuits, discontinuities, leakage or incorrect line connection G01R31/50; checking computers or computer components G06F11/00; checking static stores for correct operation G11C29/00 ; testing receivers or transmitters of transmission systems H04B17/00
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/2855 Environmental, reliability or burn-in testing
• CPC Class Codes: G01R 31/2863 Contacting devices, e.g. sockets, burn-in boards or mounting fixtures in general G01R1/04
• CPC Class Codes: G01R 31/2867 Handlers or transport devices, e.g. loaders, carriers, trays
• CPC Class Codes: G01R 31/2886 Features relating to contacting the IC under test, e.g. probe heads; chucks G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06
• CPC Class Codes: G01R 31/2889 Interfaces, e.g. between probe and tester G01R31/31905 and G01R1/07364 take precedence
• CPC Class Codes: G01R 31/2893 Handling, conveying or loading, e.g. belts, boats, vacuum fingers G01R31/2867 takes precedence; handling semiconductor devices or wafers during manufacture or treatment H01L21/67
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 22/22 Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement testing and repair of stores after manufacture including at wafer scale G11C29/00; fuses per se H01L23/525
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2225/06562 at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 24/80 Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/15151 : the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
• CPC Class Codes: H05K 2201/0133 : Elastomeric or compliant polymer elastomeric conductor H05K2201/0314
• CPC Class Codes: H05K 2201/0347 : Overplating, e.g. for reinforcing conductors or bumps; Plating over filled vias reinforcing the conductive pattern H05K3/24
• CPC Class Codes: H05K 2201/0367 : Metallic bump or raised conductor not used as solder bump solder materials or compositions and methods of application thereof H05K3/3457
• CPC Class Codes: H05K 2201/0394 : Conductor crossing over a hole in the substrate or a gap between two separate substrate parts
• CPC Class Codes: H05K 2201/09481 : Via in pad; Pad over filled via if used for surface mounting H05K1/113
• CPC Class Codes: H05K 2201/09563 : Metal filled via plated through-hole filled with insulating material H05K2201/0959
• CPC Class Codes: H05K 2203/0307 : Providing micro- or nanometer scale roughness on a metal surface, e.g. by plating of nodules or dendrites
• CPC Class Codes: H05K 2203/0723 : Electroplating, e.g. finish plating
• CPC Class Codes: H05K 3/0058 : Laminating printed circuit boards onto other substrates, e.g. metallic substrates H05K1/0281 takes precedence
• CPC Class Codes: H05K 3/0067 : onto an inorganic, non-metallic substrate
• CPC Class Codes: H05K 3/4007 : Surface contacts, e.g. bumps H05K3/4092 takes precedence; deposition of finish layers on pads H05K3/24; forming solder bumps H05K3/3457
• CPC Class Codes: H05K 3/423 : characterised by electroplating method

Abstract

A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consisting of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer, and the second half establishes electrical communication between the wafer and electrical testing equipment. A rigid substrate has conductors thereon which establish electrical contact with the wafer. The test fixture need not be opened until the burn-in and electrical testing are completed. After burn-in stress and electrical testing, it is possible to establish interconnection between the single die or separate and package dice into discrete parts, arrays or clusters, either as singulated parts or as arrays.

Claims

1. A method for performing at least one operation of a testing operation and a burn-in operation on an uncut wafer having two opposing surfaces using a first plate which includes a biasing mechanism, and a second rigid plate selectively engageable with the first plate, the second rigid plate having a plurality of contact elements extending therefrom and having a cavity for receiving the uncut wafer therein, the wafer having a plurality of semiconductor dice thereon and at least one interconnect between at least two semiconductor dice on the wafer, the method comprising:

placing the wafer, in a desired orientation, between the first plate and the second rigid plate with the plurality of contact elements on the second rigid plate engaging corresponding locations on the wafer, at least one contact element for contacting at least a portion of the interconnect between at least two semiconductor dice on the wafer; and

biasing the plurality of contact elements of the second rigid plate against a surface of the wafer by applying an elastic force to an opposing surface of the wafer with the first plate, the force caused by the biasing mechanism, and the force applied to substantially the entirety of the opposing surface.

2. The method as claimed in claim 1, wherein the wafer comprises a semiconductor wafer.

3. The method as claimed in claim 1, wherein the wafer includes an array of semiconductor dice located thereon.

4. The method as claimed in claim 1, further comprising:

aligning the first plate and the second rigid plate.