Single event upset hardened latch

• US 7,161,404 B2
• Filed: 12/19/2003
• Issued: 01/09/2007
• Est. Priority Date: 12/23/1999
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Soumyanath, Krishnamurthy, Hazucha, Peter
• Primary Examiner(s): Lam; Tuan T.
• Application Number:
  US10/742,436
• Publication Number:
  US 20040130351A1
• Time in Patent Office: 1,117 Days
• Field of Search: 327/202, 327/203, 327/206, 327/218, 327/225, 327/208, 327/209, 327/210, 327/211, 327/212, 365/154, 365/156, 365/205
• US Class Current: 327/203
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/0375 provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails digital storage cells each combining volatile and non-volatile storage properties G11C14/00
• CPC Class Codes: H03K 3/356156 with synchronous operation
• CPC Class Codes: H03K 3/356173 with synchronous operation

Abstract

A hardened latch capable of providing protection against single event upsets (SEUs) is disclosed. The hardened latch includes a first latch and a second latch that mirrors a subset of gates of the first latch. The second latch is inserted in the feedback path of the keeper circuit of the first latch and is cross-coupled with the gates of the keeper circuit of the first latch. The latch is hardened against single event upsets and an arbitrary number of successive SEUs attacking a single node, provided that the time between successive SEUs is larger than the recovery time of the latch. An alternate embodiment of the hardened latch includes a split buffer output. This embodiment is capable of reducing the propagation of erroneous transients. Another alternate embodiment of the hardened latch includes a Miller C buffer output. This embodiment is capable of reducing the propagation of erroneous transients below the level achievable in a hardened latch employing a split buffer output.

Claims

1. A latch circuit, comprising:

a first latch; and

a second latch to harden the latch circuit to a single event upset, the second latch including a transmission gate including two transistors, the transmission gate having an output port to couple to only one transistor of the first latch; and

a Miller C buffer to couple to the second latch.

2. A die comprising:

a first latch having a feedback path; and

a second latch including a transmission gate including two transistors, the transmission gate located in the feedback path to render the die immune to single event upsets attacking a single node at a time; and

a Miller C buffer to couple to the second latch.

3. A method, comprising:

setting a hardened latch having a latched node to an initial value;

receiving a single event upset at the latched node;

overriding the single event upset with a second latched value to return the output value at the latched node to the initial value; and

presenting the output value at a Miller C buffer.

4. The method of claim 3, further comprising:

receiving a series of single event upsets at the latched node; and

overriding at least about 50% of the series of single event upsets with a second latched value to return the output value at the latched node to the initial value.

5. A method of claim 3, further comprising:

receiving ionizing radiation at the latched node.

6. The method of claim 3, further comprising:

propagating less than about 50% of spurious transients to the Miller C buffer.

7. A system, comprising:

a bus;

at least one electronic unit to couple to the bus; and

a processor to couple to the bus, the processor including a plurality of hardened latches for reducing a plurality of spurious transients induced by at least one single event upset event, wherein at least one of the plurality of hardened latches includes a Miller C output buffer.

8. The system of claim 7, wherein at least one of the plurality of hardened latches comprises:

a first latch; and

a second latch to harden the at least one of the plurality of hardened latches to a single event upset, the second latch including a transmission gate having an output port to couple to only one transistor of the first latch.

9. The system of claim 7, wherein at least one of the plurality of hardened latches comprises:

a first latch having a feedback path; and

a second latch including a transmission gate including two transistors, the transmission gate located in the feedback path to render the processor immune to single event upsets attacking a single node at a time.

10. The system of claim 7, wherein at least one of the plurality of hardened latches comprises:

an input gate;

a first latch having a first set of gates, the first latch to couple to the input gate;

a second latch having a second set of gates identical to the first set of gates, the second latch to couple to the first latch and the input gate.