Apparatus and method for improving resolution of a current mode driver

• US 7,161,513 B2
• Filed: 12/20/2000
• Issued: 01/09/2007
• Est. Priority Date: 10/19/1999
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Chau, Pak Shing, Werner, Carl
• Primary Examiner(s): NGUYEN, LINH V
• Application Number:
  US09/742,250
• Publication Number:
  US 20020091948A1
• Time in Patent Office: 2,211 Days
• Field of Search: 341/119, 341/118, 341/120, 341144-172, 702/129, 702/130, 702/132, 702/99
• US Class Current: 341/119
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 2207/108 Wide data ports
• CPC Class Codes: G11C 27/02 Sample-and-hold arrangements G11C27/04 takes precedence
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/106 Data output latches
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1084 Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1087 Data input latches
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/0282 Provision for current-mode coupling
• CPC Class Codes: H04L 25/0298 Arrangement for terminating transmission lines
• CPC Class Codes: H04L 25/08 Modifications for reducing interference; Modifications for reducing effects due to line faults ; Receiver end arrangements for detecting or overcoming line faults
• CPC Class Codes: H04L 25/4902 Pulse width modulation; Pulse position modulation
• CPC Class Codes: H04L 7/0332 with an integrator-detector

Abstract

A method for improving resolution of a current mode driver. The current mode driver is operable to provide an output that falls within a predetermined range. An embodiment of the method includes sensing a condition, such as a process condition, a voltage condition and a temperature condition. A full scale current of a digital-to-analog converter is adjusted in accordance with the condition. A current control signal is set based on an output of the digital-to-analog converter. The sensing step may include measuring a process, voltage or temperature sensitive DC parameter. Alternatively, the sensing step may include sensing a process, voltage or temperature sensitive AC parameter.

Claims

1. A method for improving resolution of a current mode driver, where the current mode driver is operable to provide an output that falls within a predetermined range, the method comprising:

sensing at least one of a process condition, a voltage condition and a temperature condition with a PVT detector;

adjusting a full scale current of a DAC in accordance with an output of the PVT detector; and

setting a current control signal based on an output of the DAC, the current control signal being applied to the current mode driver to improve resolution of the current mode driver, wherein the current control signal for transistors in the current mode driver includes a plurality of bits;

wherein the sensing comprises;

applying a PVT independent current to a PVT sensitive load; and

detecting a voltage drop across the PVT sensitive load.

2. The method as claimed in claim 1, wherein the sensing comprises sensing a PVT sensitive DC parameter.

3. The method as claimed in claim 1, wherein the sensing comprises sensing a PVT sensitive AC parameter.

4. A method for improving resolution of a current mode driver, where the current mode driver is operable to provide an output that falls within a predetermined range, the method comprising:

sensing at least one of a process condition, a voltage condition and a temperature condition with a PVT detector;

adjusting a full scale current of a DAC in accordance with an output of the PVT detector; and

setting a current control signal based on an output of the DAC, the current control signal being applied to the current mode driver to improve resolution of the current mode driver, wherein the current control signal for transistors in the current mode driver includes a plurality of bits;

wherein the sensing comprises;

applying a pulse in parallel to a delay line and a first plurality of latches, wherein the delay line comprises a second plurality of delay stages;

coupling an output of a subset of the plurality of delay stages to an input of a corresponding latch from the plurality of latches; and

decoding an output from the plurality of latches.

5. In an output driver that is operable to provide a multi-PAM output having at least two levels, wherein the output is set in accordance with a current control signal, a method of improving resolution of the output driver, the method comprising the steps of:

applying the current control signal to cause the output driver to sink a full scale current;

providing a PVT detector to sense a characteristic that comprises at least one of a process condition, a voltage condition and a temperature condition;

generating a full scale current adjustment signal at the PVT detector;

applying a full scale current adjustment signal to alter the full scale current of the output driver;

applying the current control signal to cause the output driver to sink a second current, wherein the second current is less than the full scale current;

sensing, at the PVT detector, at least one of a process condition, a voltage condition and a temperature condition;

generating a second current adjustment signal at the PVT detector;

applying the second current adjustment signal to alter the second current of the output driver; and

calibrating the altered full scale current of the output drier and the altered second current of the output driver by comparing the altered full scale current with a first reference and comparing the altered second current with a second reference.

6. The method of improving resolution of an output driver as claimed in claim 5, wherein the step of applying the full scale current adjustment signal comprises coupling the adjustment signal to a digital-to-analog converter.

7. The method of improving resolution of an output driver as claimed in claim 6, wherein the adjustment signal to a two-bit signal and the digital-to-analog converter has at least two inputs.

8. The method of improving resolution of an output driver as claimed in claim 6, wherein the digital-to-analog converter provides an output signal in response to the adjustment signal.

9. A method of improving resolution of a current mode driver, comprising the steps of:

applying a first current control signal to a digital-to-analog converter, the digital-to-analog converter providing a first output in response thereto;

applying the first output as a gate voltage to control a full scale current of an output driver;

calibrating the output driver by comparing a second output, which is provided by the output driver, with a reference; and

augmenting the first current control signal when the second output differs from the reference.

10. The method as claimed in claim 9, wherein the step of calibrating the output driver comprises deriving the second input from a signal provided directly to the output driver.

11. The method as claimed in claim 10, wherein the step of deriving the second output comprises applying the signal to a resistor divider.

12. The method as claimed in claim 10, wherein the step of deriving the second output comprises applying the signal to a transconductance stage.

13. The method as claimed in claim 10, wherein the step of deriving the second output comprises applying the signal to a switched capacitor circuit.

14. The method as claimed in claim 9, wherein the first current control signal is applied under user control.

15. A method for improving resolution of a current mode driver, where the current mode driver is operable to provide an output that falls within a predetermined range, the method comprising:

sensing at least one of a process condition, a voltage condition and a temperature condition with a PVT detector;

adjusting a full scale current of a DAC in accordance with an output of the PVT detector; and

setting a current control signal based on an output of the DAC, the current control signal being applied to the current mode driver to improve resolution of the current mode driver, wherein the current control signal for transistors in the current mode driver includes a plurality of bits;

wherein the current mode driver is a multi-PAM signal generator coupled to a bus, the multi-PAM signal generator uses pulses having a plurality of sets of signal amplitudes to encode signals, and wherein a respective set of signal amplitudes in the plurality of sets of signal amplitudes has at least two signal levels.

16. The method of claim 15, wherein the sensing, adjusting and setting steps occur during a power-up sequence for the multi-PAM signal generator.

17. The method of claim 15, wherein the adjusting and setting steps occur in response to a triggering event after power-up.