Memory device tester and method for testing reduced power states
First Claim
1. A memory device tester comprising:
- a receptacle for receiving a memory device;
at least one control bus coupled to the receptacle for communicating with the memory device; and
a processing unit coupled to the at least one control bus for sending a plurality of commands to the memory device, the plurality of commands comprising;
a first command adapted to cause the memory device to enter a reduced power state;
a first current calibration sequence;
a second command adapted to cause the memory device to leave the reduced power state; and
a second current calibration sequence.
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Accused Products
Abstract
A memory device tester capable of testing for proper operation of reduced power states in memory devices. The memory device tester can include a processor or a state machine, each configured to send commands to the memory device, and to compare results. An example of a memory device that can be tested by the memory device tester is a Direct Rambus Dynamic Random Access Memory (DRDRAM). The described processing systems and other circuits can test a DRDRAM for proper operation in a standby (STBY) state. When the DRDRAM is in STBY, the column decoder is shut off to conserve power, and the DRDRAM should not respond to column packets on the column control bus. The method and apparatus provide for testing that the column decoder is shut off when in STBY with no banks active, which is the recommended usage pattern for the part.
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Citations
35 Claims
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1. A memory device tester comprising:
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a receptacle for receiving a memory device; at least one control bus coupled to the receptacle for communicating with the memory device; and a processing unit coupled to the at least one control bus for sending a plurality of commands to the memory device, the plurality of commands comprising; a first command adapted to cause the memory device to enter a reduced power state; a first current calibration sequence; a second command adapted to cause the memory device to leave the reduced power state; and a second current calibration sequence. - View Dependent Claims (4, 5, 6, 7, 8, 9)
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2. A memory device tester comprising:
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a receptacle for receiving a memory device having multiple banks; at least one control bus coupled to the receptacle for communicating with the memory device; a data bus for coupling to the memory device; and a processing unit coupled to the at least one control bus for sending a plurality of commands to the memory device, wherein at least one of the commands is adapted to cause the memory device to output a data value on the data bus regardless of whether any of the multiple banks are active. - View Dependent Claims (10, 11, 12, 13, 14)
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3. A memory device tester comprising:
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a receptacle for receiving a memory device; at least one control bus coupled to the receptacle for communicating with the memory device; a data bus for coupling to the memory device; and a processing unit coupled to the at least one control bus, the processing unit adapted to; send a first command adapted to cause the memory device to enter a reduced power state; send a second command adapted to request data from the memory device; and sample the data bus to determine if the data bus is in an undriven state. - View Dependent Claims (15, 16, 17, 18, 19)
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20. A memory device tester comprising:
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a receptacle for receiving a memory device; at least one control bus coupled to the receptacle for communicating with the memory device; a data bus for coupling to the memory device; and a processing unit coupled to the at least one control bus, the processing unit adapted to; send a command adapted to cause the memory device to enter a reduced power state; send a command adapted to request data from the memory device; send a command adapted to compare a data value on the data bus against an expected value; send a command adapted to cause the memory device to leave the reduced power state; send a command adapted to request data from the memory device; and send a command adapted to compare a data value on the data bus against an expected value. - View Dependent Claims (21, 22, 23)
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24. A memory device tester comprising:
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a receptacle for receiving a memory device; a row control bus and a column control bus coupled to the receptacle for communicating with the memory device; a data bus for coupling to the memory device; and a processing unit coupled to the row control bus and the column control bus for sending a plurality of commands to the memory device, wherein at least one of the commands is adapted to cause the memory device to output a data value on the data bus regardless of whether any of the multiple banks are active. - View Dependent Claims (25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35)
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Specification