Delay locked loop synthesizer with multiple outputs and digital modulation
First Claim
Patent Images
1. A circuit, comprising:
- a delay locked loop having a delay line with a plurality of tap outputs;
a first tap selection circuit that produces a first set of tap addresses to select a first set of the plurality of tap outputs from the delay line according to a first timing to produce a first output signal;
a second tap selection circuit that produces a second set of tap addresses to select a second set of the plurality of tap outputs from the delay line according to a second timing to produce a second output signal;
a modulator combining the first and second output signals to produce a modulated output signal; and
wherein the modulator frequency-modulates the first output signal with the second output signal.
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Abstract
A delay locked loop circuit (200) in which multiple outputs are produced. A single delay line (24) is shared among multiple tap selection circuits (256A, 265B, 265C). Fixed phase shifts (412) can be introduced between multiple outputs. A modulating signal can be used in the tap selection processing to produce digital amplitude, frequency and/or phase modulation.
33 Citations
43 Claims
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1. A circuit, comprising:
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a delay locked loop having a delay line with a plurality of tap outputs; a first tap selection circuit that produces a first set of tap addresses to select a first set of the plurality of tap outputs from the delay line according to a first timing to produce a first output signal; a second tap selection circuit that produces a second set of tap addresses to select a second set of the plurality of tap outputs from the delay line according to a second timing to produce a second output signal; a modulator combining the first and second output signals to produce a modulated output signal; and wherein the modulator frequency-modulates the first output signal with the second output signal.
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2. A circuit, comprising:
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a delay locked loop having a delay line with a plurality of tap outputs; a first tap selection circuit that produces a first set of tap addresses to select a first set of the plurality of tap outputs from the delay line according to a first timing to produce a first output signal; a second tap selection circuit that produces a second set of tap addresses to select a second set of the plurality of tap outputs from the delay line according to a second timing to produce a second output signal; a modulator combining the first and second output signals to produce a modulated output signal; and wherein the modulator phase-modulates the first output signal with the second output signal.
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3. A circuit, comprising:
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a delay locked loop having a delay line with a plurality of tap outputs; a first tap selection circuit that produces a first set of tap addresses to select a first set of the plurality of tap outputs from the delay line according to a first timing to produce a first output signal; a second tap selection circuit that produces a second set of tap addresses to select a second set of the plurality of tap outputs from the delay line according to a second timing to produce a second output signal; a modulator combining the first and second output signals to produce a modulated output signal; and wherein the modulator amplitude-modulates the first output signal with the second output signal.
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4. A circuit, comprising:
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a delay locked loop having a delay line with a plurality of tap outputs; a first tap selection circuit that produces a first set of tap addresses to select a first set of the plurality of tap outputs from the delay line according to a first timing to produce a first output signal; a second tap selection circuit that produces a second set of tap addresses to select a second set of the plurality of tap outputs from the delay line according to a second timing to produce a second output signal; a tap selection processor that selects the first set of the plurality of tap outputs from the delay line according to the first timing, and selects the second set of the plurality of tap outputs from the delay line according to the second timing, the tap selection processor comprising; a frequency accumulator receiving an integer part K of K.C where K.C=Fout/Fref, where Fout is a desired output frequency and Fref is a reference clock frequency, and wherein the frequency accumulator is clocked by Fref; and a phase accumulator that receives the fractional part C of K.C, wherein the phase accumulator is clocked by an overflow of the frequency accumulator, and wherein the frequency accumulator produces the first set of the plurality of tap output addresses as an output thereof; a first demultiplexer responsive to the tap selection processor to selectively route the selected first set of the plurality of tap outputs to a common node to produce the first output signal; and a second demultiplexer responsive to the tap selection processor to selectively route the selected second set of the plurality of selected tap outputs to another common node to produce the second output signal.
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5. A circuit, comprising:
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a delay locked loop having a delay line with a plurality of tap outputs; a first tap selection circuit that produces a first set of tap addresses to select a first set of the plurality of tap outputs from the delay line according to a first timing to produce a first output signal, the first tap selection circuit further comprising; a first tap selection processor that selects the first set of the plurality of tap outputs from the delay line according to the first timing; and a first demultiplexer responsive to the first tap selection processor to selectively route the selected first set of tap outputs to a common node to produce the first output signal; a second tap selection circuit that produces a second set of tap addresses to select a second set of the plurality of tap outputs from the delay line according to a second timing to produce a second output signal, the second tap selection circuit further comprising; a second tap selection processor that selects the second set of the plurality of tap outputs from the delay line according to the second timing; and a second demultiplexer responsive to the second tap selection processor to selectively route the selected second set of tap outputs to another common node to produce the second output signal; and wherein the first tap selection processor comprises; a frequency accumulator receiving an integer part K of K.C where K.C=Fout/Fref, where Fout is a desired output frequency and Fref is a reference clock frequency, and wherein the frequency accumulator is clocked by Fref; and a phase accumulator that receives the fractional part C of K.C, wherein the phase accumulator is clocked by an overflow of the frequency accumulator, and wherein the frequency accumulator produces the first set of the plurality of tap output addresses as an output thereof. - View Dependent Claims (6)
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7. A circuit for producing two output signals having frequency Fout and differing by a phase shift, comprising:
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a delay locked loop having a plurality of addressable tap outputs; a tap selection circuit that selects a first sequence of tap addresses Cja from the addressable tap outputs; an adder that adds a normalized phase shift component Φ
=α
/ (2 π
) (α
=a desired phase shift in radians) to the first sequence of tap addresses Cja to produce a second sequence of tap addresses Cjb, where C is the fractional part of K.C in K.C=Fout/Fref, and Fref being a reference clock frequency; anda first multiplexer and a second multiplexer, wherein the first sequence of tap addresses Cja are applied to the first multiplexer to produce a first output signal Fouta, and wherein the second sequence of tap addresses Cjb are applied to the second multiplexer to produce a second output signal Foutb, and wherein Fouta differs from Foutb by the desired phase shift. - View Dependent Claims (8, 9)
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10. A circuit for producing two output signals differing by a phase shift, comprising:
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a delay locked loop having a plurality of addressable delay line tap outputs, the delay locked loop synthesizing the output signals at a frequency Fout, with K.C=Fout/Fref, and Fref being a reference clock frequency; a tap selection circuit that selects a sequence of tap addresses Cja from the plurality of addressable delay line tap outputs; a first multiplexer, wherein the sequence of tap addresses Cja are applied to a plurality of inputs of the first multiplexer to produce a first output signal Fouta; a second multiplexer, wherein the sequence of tap addresses Cja are added to a delay factor α
/(2π
) where α
is a desired phase shift in radians and applied to a plurality of inputs of the second multiplexer to produce a second output signal Foutb; andwherein the first and second multiplexers each comprise N;
1 multiplexers having N inputs.- View Dependent Claims (11, 12, 13)
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14. A digital frequency modulator, comprising:
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a delay locked loop having a delay line with a plurality of tap outputs; a tap selection processor that selects, from the delay line with the plurality of tap outputs, a sequence of time varying tap addresses Cj(t) that vary in time in accordance with a modulating signal m(t); and a multiplexer circuit, and wherein the time varying tap addresses Cj(t) are applied to the multiplexer circuit to select a time varying sequence of tap outputs as a frequency modulated output signal Fout(t) wherein the tap selection processor comprises an integrator that integrates the modulating signal m(t) and an adder that adds the integrated modulating signal m(t) to a selected sequence of tap addresses Cj to produce Cj(t). - View Dependent Claims (15, 16, 17, 18)
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19. A digital amplitude modulator, comprising:
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a delay locked loop having a delay line with a plurality of tap outputs; a tap selection processor that selects, from the delay line with the plurality of tap outputs, a sequence of time varying tap addresses Cj(t) that vary in time in accordance with a modulating signal m(t); a multiplexer circuit, and wherein the time varying tap addresses Cj(t) are applied to the multiplexer circuit to select a time varying sequence of tap outputs as an output signal Fout(t); and wherein the tap selection processor comprises; a first adder that adds the modulating signal m(t) to a selected sequence of tap addresses Cja to produce a first sequence of time varying tap addresses Cjb(t); a second adder that subtracts the modulating signal m(t) from the selected sequence of tap addresses Cja to produce a second sequence of time varying tap addresses Cjc(t); and wherein Cj(t) comprises Cjb(t) and Cjc(t); and
wherein the multiplexer circuit comprises;a first multiplexer receiving the first sequence of time varying tap addresses Cjb(t) to produce a first output signal V1(t); and a second multiplexer receiving the second sequence of time varying tap addresses Cjc(t) to produce a second output signal V2(t); and further comprising; a summation circuit that adds V1(t) to V2(t) to obtain an amplitude modulated output signal V(t). - View Dependent Claims (20, 21, 22, 23, 24, 25, 26)
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27. A method of producing multiple output frequencies using a delay locked loop having a delay line with a plurality of tap outputs, comprising:
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selecting a first sequence of the tap outputs from the delay line having the plurality of tap outputs according to a first timing to produce a first output signal Fout1; selecting a second sequence of the tap outputs from the delay line having the plurality of tap outputs according to a second timing to produce a second output signal Fout2.; and applying addresses of the first sequence of tap outputs to a first multiplexer to perform selecting the first sequence of tap outputs; and applying addresses of the second sequence of tap outputs to a second multiplexer to perform selecting-the second sequence of tap outputs; and modulating the first sequence of tap outputs with the second sequence of tap outputs.
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28. A method of producing two output signals differing by a phase shift in a delay locked loop circuit having a delay line with a plurality of addressable tap outputs, comprising:
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selecting a first sequence of tap addresses Cja; adding a phase shift component Φ
to the first sequence of tap addresses Cja to produce a second sequence of tap addresses Cjb; andapplying the first sequence of tap addresses Cja to a first multiplexer to produce a first output signal Fouta; and applying the second sequence of tap addresses Cjb to a second multiplexer to produce a second output signal Foutb, and wherein Fouta differs from Foutb by a phase shift related to Φ
. - View Dependent Claims (29, 30)
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31. A method of producing two output signals differing by a phase shift using a delay locked loop having a plurality of addressable delay line tap outputs, comprising:
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selecting a sequence of tap addresses Cja from the delay locked loop having a delay line providing the plurality of addressable delay line tap outputs; applying the sequence of tap addresses Cja to a plurality of inputs of a first multiplexer to produce a first output signal Fouta; and applying the sequence of tap addresses Cja to a plurality of inputs of a second multiplexer to produce a second output signal Foutb; wherein Fout1 differs from Fout2 by the phase shift, and wherein the phase shift is determined by a constant difference in address location selected by the sequence of tap addresses Cja between the first and second multiplexers. - View Dependent Claims (32, 33, 34, 35)
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36. A method of providing digital frequency modulation in a delay locked loop circuit having a delay line with a plurality of tap outputs, comprising:
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selecting a sequence of time varying tap addresses Cj(t) that vary in time in accordance with a modulating signal m(t), wherein the selecting comprises; integrating the modulating signal m(t); and adding the integrated modulating signal m(t) to a selected sequence of tap addresses Cj to produce Cj(t); and applying the time varying tap addresses Cj(t) to a multiplexer circuit to select a time varying sequence of tap outputs as a frequency modulated output signal Fout(t).
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37. A method of providing digital amplitude modulation in a delay locked loop circuit having a delay line with a plurality of tap outputs, comprising:
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selecting a sequence of time varying tap addresses Cj(t) that vary in time in accordance with a modulating signal m(t), wherein the selecting comprises; adding the modulating signal m(t) to a selected sequence of tap addresses Cja to produce a first sequence of time varying tap addresses Cjb(t); and subtracting the modulating signal m(t) from the selected sequence of tap addresses Cja to produce a second sequence of time varying tap addresses Cjc(t), wherein Cj(t) comprises Cjb(t) and Cjc(t); and applying the time varying tap addresses Cj(t) to a multiplexer circuit to select a time varying sequence of tap outputs as an amplitude modulated output signal Fout(t). - View Dependent Claims (38, 39, 40, 41)
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42. A method of selecting delay line taps to produce an output signal from a delay locked loop, comprising:
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computing an tap address P.Q where P is an integer part and Q is a fractional part; and selecting a delay line tap address of P during a portion of an operational cycle and of P+1 during a remainder of the operational cycle, with the regularity of selection of P and P+1 determined by an algorithm that establishes an average value of the tap address as approximately P.Q. - View Dependent Claims (43)
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Specification