Phase-interpolator based PLL frequency synthesizer

• US 7,162,002 B2
• Filed: 10/31/2002
• Issued: 01/09/2007
• Est. Priority Date: 03/01/2002
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Wakayama, Myles, Chen, Chun-Ying, Le, Michael Q
• Primary Examiner(s): Ghayour; Mohammed
• Assistant Examiner(s): Malek; Leila
• Application Number:
  US10/284,341
• Publication Number:
  US 20030165209A1
• Time in Patent Office: 1,531 Days
• Field of Search: 375/376, 375/371, 375/362, 375/373, 375/374, 375/375, 455/260
• US Class Current: 375/376
• CPC Class Codes: G11B 20/1403 characterised by the use of two levels
• CPC Class Codes: H03L 7/081 provided with an additional controlled phase shifter H03L7/0998 takes precedence
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/0996 Selecting a signal among the plurality of phase-shifted signals produced by the ring oscillator
• CPC Class Codes: H03L 7/0998 using phase interpolation
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence
• CPC Class Codes: H04L 7/0025 interpolation of clock signal
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

A phase lock loop frequency synthesizer includes a phase rotator in the feedback path of the PLL. The PLL includes a phase detector, a low pass filter, a charge pump, a voltage controlled oscillator (“VCO”), and a feed back path connecting output of the VCO to the phase detector. The feedback path includes a phase rotator connected to the output of the VCO and to an input of a frequency divider. Coarse frequency control is implemented by adjusting the input reference frequency to the phase detector or by adjusting the divider ratio of the frequency divider. Fine frequency control is achieved by increasing or decreasing the rotation speed of the phase rotator. The phase rotator constantly rotates phase of the VCO output, thereby causing a frequency shift at the output of the phase rotator. The rotation speed of the phase rotator is controlled by an accumulator and a digital frequency control word. Any high frequency noise generated by the phase rotator is rejected by the PLL by properly setting the PLL bandwidth so that the noise falls outside the bandwidth of the PLL. Therefore, a low noise synthesized output from the VCO is generated.

Claims

1. A frequency synthesizer, comprising:

a phase detector;

a charge pump coupled to an output of said phase detector;

a low pass filter coupled to an output of said charge pump;

a voltage controlled oscillator (“

VCO”

) coupled to an output of said low pass filter; and

a feedback path coupled between an output of said VCO and said phase detector, wherein said feedback path includes a phase rotator capable of fine tuning an output frequency of said VCO responsive to a frequency of an input clock, by adjusting a rotation speed of said phase rotator.

2. The frequency synthesizer of claim 1, wherein said feedback path further comprises an accumulator coupled to said phase rotator, wherein said accumulator supplies said input clock to said phase rotator.

3. The frequency synthesizer of claim 2, wherein said phase rotator finely tunes said VCO output frequency upon application of said input clock.

4. The frequency synthesizer of claim 2, wherein said accumulator receives a frequency control word signal and said VCO output frequency.

5. The frequency synthesizer of claim 2, wherein said accumulator receives a frequency control word signal and an external clock frequency.

6. The frequency synthesizer of claim 4, wherein a frequency of said input clock determines said rotation speed of said phase rotator.

7. The frequency synthesizer of claim 1, wherein said VCO output includes a plurality of taps producing a plurality of VCO output phases.

8. The frequency synthesizer of claim 7, wherein said phase rotator includes:

means for weighting said plurality of VCO output phases over time responsive to said input clock; and

means for combining said weighted VCO output phases to produce an output phase of said phase rotator, said output phase rotating responsive to a frequency of said input clock.

9. The frequency synthesizer of claim 7, wherein said phase rotator includes:

a plurality of differential amplifiers receiving said plurality of VCO output phases;

a differential output that combines respective outputs of said differential amplifiers;

a plurality of digital-to-analog converters (DACs) arranged in groups, each group of DACs supplying bias current to a corresponding differential amplifier;

a shift register that receives said input clock having a plurality of outputs that switch said plurality of digital-to-analog converters (DACs) responsive to said input clock.

10. The frequency synthesizer of claim 9, wherein a frequency of said input clock determines a switching speed of said DACs, and thereby said rotation speed of a phase of said differential output.

11. The frequency synthesizer of claim 9, wherein each of said DACs includes a current source that is series-connected with a switch, said switch controlled by a respective output of said shift register.

12. The frequency synthesizer of claim 9, wherein said output frequency of said VCO is determined according to the following equation:

$f_{\mathrm{CLK\_VCO}}=N*f_{\mathrm{CLK\_REF}}\pm <br><br>\frac{f_{\mathrm{CLK\_PI}}}{2^M}$

wherein,

f<sub>CLK—

REF</sub> is a frequency of a reference clock received by said phase detector;

f<sub>CLK—

PI</sub> is said frequency of said input clock; and

M is the number of bits in said digital-to-analog converters in said DAC groups.

13. The frequency synthesizer of claim 9, wherein said feedback path further comprises an accumulator coupled to said phase rotator, wherein said accumulator supplies said input clock to said phase rotator, and wherein said output frequency of said VCO is determined according to the following equation:

$f_{\mathrm{CLK\_VCO}}=N*f_{\mathrm{CLK\_REF}}\pm <br><br>\frac{\mathrm{FCW}}{2^{L+M}}*f_{\mathrm{CLK\_VCO}}$

wherein,

f<sub>CLK—

REF</sub> is a frequency of a reference clock received by said phase detector;

L is the number of bits associated with said accumulator; and

M is the number of bits in said digital-to-analog converters in said DAC groups

FCW is the frequency control word signal.

14. A method of frequency tuning a frequency synthesizer having a phase lock loop including a phase detector, a voltage controlled oscillator (“

VCO”

), and a feedback path between an output of the VCO and the phase detector, comprising the steps of;

receiving an input reference signal having a reference phase and frequency;

generating a VCO output signal based on the input reference signal;

feeding the VCO output signal through the feedback path to the phase detector; and

phase rotating the VCO output signal in the feedback path at a constant rate to perform fine frequency tuning the VCO output signal, wherein the constant rate determines a fine frequency shift of the VCO, wherein the phase rotating step includes the step of determining a rotation speed of the phase rotator based on a frequency of the VCO output signal and a desired frequency for the VCO.

15. The method of claim 14, further comprising the step of adjusting a divider ratio of a frequency divider in the feedback path to perform coarse frequency tuning.

16. The method of claim 14, further comprising the step of adjusting the reference signal frequency to perform coarse frequency tuning.

17. The method of claim 14, wherein said VCO output signal is taken from a plurality of taps producing a plurality of VCO output phases.

18. The method of claim 14, wherein said VCO output signal includes a plurality VCO output phases, wherein said step of phase rotating includes the steps:

weighting the plurality of VCO output phases over time responsive to a input clock; and

combining the weighted VCO outputs to produce an output phase, wherein the output phase rotating responsive to a frequency of the input clock.

19. A frequency synthesizer, comprising:

a phase detector;

a charge pump coupled to an output of said phase detector;

a low pass filter coupled to an output of said charge pump;

a voltage controlled oscillator (“

VCO”

) coupled to an output of said low pass filter; and

a feedback path coupled between an output of said VCO and said phase detector, wherein said feedback path includes

a phase rotator that fine tunes an output frequency of said VCO output based on a rotation speed of the phase rotator, said rotation speed responsive to a frequency of an input clock, and

a frequency divider that coarse tunes said output frequency of said VCO by adjusting a divider ratio of said frequency divider.

20. The phase lock loop frequency synthesizer of claim 19, wherein said VCO output includes a plurality of taps producing a plurality of VCO output phases.

21. The phase lock loop frequency synthesizer of claim 20, wherein said phase rotator includes:

a plurality of differential amplifiers receiving said plurality of VCO output phases;

a differential output that combines respective outputs of said differential amplifiers;

a plurality of digital-to-analog converters (DACs) arranged in groups, each group of DACs supplying bias current to a corresponding differential amplifier;

a shift register that receives said input clock having a plurality of outputs that switch said plurality of digital-to-analog converters (DACs) responsive to said input clock.