Method and apparatus for driving multiple peripherals with different clock frequencies in an integrated circuit

• US 7,162,003 B2
• Filed: 01/13/2005
• Issued: 01/09/2007
• Est. Priority Date: 01/27/2004
• Status: Active Grant

• Current Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Original Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Inventors: Vergnes, Alain, Lardy, Olivier
• Primary Examiner(s): Corrielus; Jean B.
• Application Number:
  US11/036,471
• Publication Number:
  US 20050165996A1
• Time in Patent Office: 726 Days
• Field of Search: 375/316, 375/377, 375/354, 713/500, 713/600, 710305-306, 710/308, 710/8, 710/10, 710/12, 710/3, 710/6, 710/36, 710/311, 710/315, 710/313
• US Class Current: 375/377
• CPC Class Codes: G06F 13/4217 with synchronous protocol
• CPC Class Codes: G06F 13/423 with synchronous protocol
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The invention is a system for selecting a peripheral, the peripheral receiving a first clock frequency. The invention comprises the following. A processing circuit receives a second clock frequency, where the first and second clock frequencies are different. The processing circuit is configured to transmit a select signal. A bridge circuit is coupled to the processing circuit and the peripheral, and is configured to receive the select signal and transmit a peripheral select signal to the peripheral. The bridge circuit is further configured to receive the second clock frequency but not the first clock frequency. A counter is coupled to the bridge circuit and is configured to process a count, the count being a predetermined number and based on the value of the first frequency.

Claims

1. A system for selecting a first peripheral and a second peripheral, the first peripheral receiving a first clock frequency and the second peripheral receiving a second clock frequency, the first and second clock frequencies differing, in an integrated circuit including a processing circuit configured to receive the first clock frequency, transmit a select signal and an address signal, comprising:

a bridge circuit coupled to the processing circuit, the first peripheral and the second peripheral, and configured to receive the select signal and the address signal and transmit a first peripheral select signal to the first peripheral and a second peripheral select signal to the second peripheral, the bridge circuit comprising a counter,

wherein the counter is configured to process a count, the count being a predetermined number and based on whether the address signal indicates a first address and the select signal indicates that access is required to the first address, which is associated with the first peripheral, or to a second address, which is associated with the second peripheral, wherein the count differs for the first and second addresses, wherein the bridge circuit asserts the first peripheral and the second peripheral for a period of time based on the value of the count.

2. The system of claim 1, the bridge circuit further comprising:

an address decoder configured to receive the select signal and address signal and determine whether the address signal is associated with the first or second peripheral.

3. The system of claim 2, the bridge circuit further comprising:

a peripheral select circuit coupled to the address decoder and configured to generate the first peripheral select signal and the second peripheral select signal based on the first or second address signal, wherein if the address signal indicates the first address then the peripheral select circuit asserts the first peripheral for a first number of clock cycles, and if the address signal indicates the second address then the peripheral select circuit asserts the second peripheral for a second number of clock cycles.

4. The system of claim 3 wherein a ratio of the period of time for which the first peripheral is asserted to the period of time for which the second peripheral is asserted is equal to a ratio of the first clock frequency to the second clock frequency.

5. The system of claim 4 wherein the first number of clock cycles equals the second number of clock cycles.

6. The system of claim 3 wherein the count is equal to the number of clock cycles that the peripheral select circuit asserts the first and second peripherals.

7. The system of claim 6 wherein a ratio of the count for asserting the first peripheral to the count for asserting the second peripheral is equal to a ratio of the first clock frequency to the second clock frequency.

8. The system of claim 3, the bridge circuit further comprising:

a select circuit configured to receive an assert signal from the peripheral select circuit indicating whether the first peripheral or the second peripheral is asserted, the select circuit further configured to select the count based on the assert signal;

the counter coupled to the select circuit and configured to track passage of a number of clock cycles based on the first clock frequency; and

a compare circuit coupled to the counter and configured to receive the count and reset the counter, wherein the counter is configured to remain enabled until the counter has tracked passage of a number of clock cycles indicated by the count at which point the compare circuit is configured to transmit a deassert signal that causes the peripheral select circuit to deassert the first or second peripheral.

9. The system of claim 8 wherein a ratio of the number of clock cycles indicated by the count for asserting the first peripheral to the number of clock cycles indicated by the count for asserting the second peripheral is equal to a ratio of the first clock frequency to the second clock frequency.

10. The system of claim 8 further comprising:

a configuration register coupled to the counter and configured to receive the count for the second address, wherein the count for the first address is based on the number of clock cycles, at the first clock frequency, to transmit the first peripheral select signal.

11. The system of claim 10 wherein the configuration register is further configured such that the count for the second address is based on the number of clock cycles, at the first clock frequency, to transmit the second peripheral select signal.

12. The system of claim 8, the configuration register further comprising:

a multiplexer configured to receive the count and the second address; and

a flip-flop coupled to the multiplexer and configured to hold the count, wherein the configuration register is configured to receive and transmit the count if the select signal matches an address other than the first address.

13. A method of selecting, in an integrated circuit, a first peripheral receiving a first clock cycle and a second peripheral receiving a second clock cycle, the method comprising:

receiving the first clock cycle in a processing circuit;

transmitting a select signal from the processing circuit;

transmitting an address signal from the processing circuit;

receiving the select and address signals at a bridge circuit, the bridge circuit comprising a counter and coupled to the processing circuit, the first peripheral and the second peripheral;

determining whether the address signal is associated with the first or second peripheral;

transmitting a first peripheral select signal to the first peripheral;

processing a first count in the counter, the first count associated with the first peripheral;

transmitting a second peripheral select signal to the second peripheral; and

processing a second count in the counter, the second count associated with the second peripheral, wherein the second count differs from the first count and is predetermined.

14. The method of claim 13, further comprising:

tracking passage of clock cycles based on the first clock frequency;

asserting the first peripheral for a period of time based on the first count and the first clock frequency; and

asserting the second peripheral for a period of time based on the second count and the first clock frequency.

15. The method claim 14 wherein a ratio of the period of time for which the first peripheral is asserted to the period of time for which the second peripheral is asserted is equal to a ratio of the first clock frequency to the second clock frequency.

16. The method of claim 14, further comprising:

comparing the first count with the passage of clock cycles based on the first clock frequency; and

comparing the second count with the passage of clock cycles based on the first clock frequency.

17. A system for selecting a peripheral, the peripheral receiving a first clock frequency, in an integrated circuit comprising:

a processing circuit configured to receive a second clock frequency and transmit a select signal and an address signal, the first and second clock frequencies differing;

a bridge circuit coupled to the processing circuit and the peripheral, and configured to receive the select and address signals and transmit a peripheral select signal to the peripheral, the bridge circuit further configured to receive the second clock frequency but not the first clock frequency, the bridge circuit comprising a counter,

wherein the counter is configured to process a count, the count being a predetermined number and based on the ratio between the first clock frequency and the second clock frequency.