Dynamically adaptable semiconductor parametric testing

• US 7,162,386 B2
• Filed: 04/25/2002
• Issued: 01/09/2007
• Est. Priority Date: 04/25/2002
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Blunn, Robert G., Velichko, Sergey A., Dorough, Michael J.
• Primary Examiner(s): Barlow; John
• Assistant Examiner(s): Washburn; Douglas N.
• Application Number:
  US10/133,685
• Publication Number:
  US 20030212523A1
• Time in Patent Office: 1,720 Days
• Field of Search: 738/659, 216/44, 250/559.29, 324/158.1, 324/765, 324/73.1, 324/724, 324/753, 324/754, 324/758, 324/763, 324/764, 356/244, 356/237.1, 382/145, 382/151, 382/149, 438/12, 438/14, 438/15, 438/17, 438/18, 438/23, 438/26, 438/106, 438/108, 438/118, 438/381, 438/597, 438/612, 438/613, 438/614, 438/618, 438/662, 438/689, 438/692, 438/708, 438/745, 438/770, 438/69, 702/81, 702/108, 702/117, 702/118, 702/119, 702/120, 702/83, 702/84, 702/121, 702/188, 714/718, 714/719, 714/724, 714/726, 714/731, 714/733, 714/745, 714/734, 714/736, 714/18, 714/19, 714/24, 714/721, 716/4, 700/121
• US Class Current: 702/119
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00

Abstract

An apparatus, method, system, and signal-bearing medium may provide multiple maps, which may include multiple probing sequences to be called upon at run-time based on statistical thresholds or other selected criteria. Each map may include a series of locations on a wafer, the tests to perform at each location, and the measured results of each test. A parametric test system may perform the test at the associated location on the wafer. If the statistical threshold is exceeded or the selected criteria is met, the current map may be abandoned in favor of a different map.

Claims

1. A method comprising:

probing a subset of test locations on a wafer using a first criteria;

probing all of the test locations using the first criteria when all of the subset of the test locations satisfy the first criteria; and

probing another subset of test locations on the wafer using a second criteria when some of the first criteria of the subset exceed a statistical threshold.

2. The method of claim 1, further comprising:

probing all of the test locations using a second criteria when all of the subset of the test locations do not satisfy the first criteria.

3. The method of claim 2, wherein the probing all of the test locations using the first criteria further comprises probing all of the test locations using a first map comprising a sequence of locations on the wafer.

4. The method of claim 2, wherein the probing all of the test locations using the first criteria further comprises testing all of the test locations using a first map comprising a sequence of tests to be performed at each of the test locations.

5. The method of claim 3, wherein probing all of the test locations using the second criteria further comprises:

switching from the first map to a second map.

6. A method comprising:

probing a subset of test locations on a wafer using a first criteria;

probing all of the test locations using the first criteria when all of the subset of the test locations satisfy the first criteria;

probing all of the test locations using a second criteria when all of the subset of the test locations do not satisfy the first criteria; and

probing all of the test locations using the second criteria when a percent badsite threshold is exceeded.

7. A method comprising:

probing a subset of test locations on a wafer using a first criteria;

probing all of the test locations using the first criteria when all of the subset of the test locations satisfy the first criteria;

probing all of the test locations using a second criteria when all of the subset of the test locations do not satisfy the first criteria; and

probing all of the test locations using the second criteria when a percent badwafer threshold is exceeded.

8. An apparatus comprising:

a parametric test control system to direct a prober to;

probe a subset of test locations on a wafer using a first map,

probe all of the test locations using the first map when all of the subset of the test locations satisfy a first criteria specified in the first map; and

probe another subset of test locations on the wafer using a second map when the first criteria exceeds a predetermined criteria threshold.

9. The apparatus of claim 8, wherein the parametric test control system is further to direct the prober to probe all of the test locations using a second map when all of the subset of the test locations do not satisfy the first criteria specified in the first map.

10. The apparatus of claim 8, wherein the first map comprises a first sequence of locations on the wafer.

11. The apparatus of claim 9, wherein the second map comprises a second sequence of locations on the wafer.

12. The apparatus of claim 9, wherein the second map comprises a sequence of tests to be performed at each of the test locations.

13. An apparatus comprising:

a parametric test control system to direct a prober to;

probe a subset of test locations on a wafer using a first map,

probe all of the test locations using the first map when all of the subset of the test locations satisfy a first criteria specified in the first map;

wherein the parametric test control system is further to direct the prober to probe all of the test locations using a second map when all of the subset of the test locations do not satisfy the first criteria specified in the first map; and

wherein the parametric test control system is further to direct the prober to probe all of the test locations using the second map when a percent badsite threshold is exceeded.

14. An apparatus comprising:

a parametric test control system to direct a prober to;

probe a subset of test locations on a wafer using a first map,

probe all of the test locations using the first map when all of the subset of the test locations satisfy a first criteria specified in the first map;

wherein the parametric test control system is further to direct the prober to probe all of the test locations using a second map when all of the subset of the test locations do not satisfy the first criteria specified in the first map; and

wherein the parametric test control system is further to direct the prober to probe all of the test locations using the second map when a percent badwafer threshold is exceeded.

15. A signal-bearing medium encoded with instructions that when executed comprise:

instructing a prober to probe first test locations on a wafer based on a first probing sequence specified in a first map; and

switching to a second probing sequence specified in a second map prior to completion of the first probing sequence when a threshold is exceeded.

16. The signal-bearing medium of claim 15, further comprising:

instructing the prober to probe second test locations on the wafer based on a second probing sequence specified in the second map.

17. A signal-bearing medium encoded with instructions that when executed comprise:

instructing a prober to probe first test locations on a wafer based on a first probing sequence specified in a first map;

switching to a second map prior to completion of the first probing sequence when a threshold is exceeded; and

wherein the switching further comprises;

switching to the second map prior to completion of the first probing sequence based on a badsite threshold being exceeded.

18. The signal-bearing medium of claim 17, wherein the switching further comprises:

determining the badsite threshold based on a number of bad sites for the first map and a total number of sites on the first map.

19. A signal-bearing medium encoded with instructions that when executed comprise:

instructing a prober to probe first test locations on a wafer based on a first probing sequence specified in a first map;

switching to a second map prior to completion of the first probing sequence when a threshold is exceeded; and

wherein the switching further comprises;

switching to the second map prior to completion of the first probing sequence based on a badwafer threshold being exceeded.

20. The signal-bearing medium of claim 19, wherein the switching further comprises:

determining the badwafer threshold based on a number of bad wafers for a lot run and a total number of wafers.

21. A signal-bearing medium encoded with a map data structure, wherein the map data structure comprises:

a sequence of locations, wherein a parametric test control system is to probe the sequence of locations on a wafer; and

a badwafer threshold, wherein the parametric test control system is to switch to a second map data structure when the badwafer threshold is exceeded.

22. The signal-bearing medium of claim 21, further comprising a badwafer inputs field.

23. The signal-bearing medium of claim 21, further comprising a badwafer outputs field.

24. The signal-bearing medium of claim 23, where in the badwafer outputs field further comprises a password lockout field, wherein the parametric test control system is to require a password to continue the probe when the badwafer threshold is exceeded and the password lockout field is set to true.

25. A signal-bearing medium encoded with a map data structure, wherein the map data structure comprises:

a sequence of locations, wherein a parametric test control system is to probe the sequence of locations on a wafer; and

a badsite threshold, wherein the parametric test control system is to switch to a second map data structure when the badsite threshold is exceeded.

26. The signal-bearing medium of claim 25, further comprising a badsite inputs field.

27. The signal-bearing medium of claim 25, further comprising a badsite outputs field.

28. The signal-bearing medium of claim 25, further comprising a multiple map outputs field.

29. The signal-bearing medium of claim 27, wherein the badsite outputs field comprises a password lockout field, wherein the parametric test control system is to require a password to continue the probe when the threshold is exceeded and the password lockout field is set to true.

30. The signal-bearing medium of claim 25, further comprising a pause field, wherein the parametric test control system is to pause the probe when the badsite threshold is exceeded and the pause field is set to true.

31. A method comprising:

moving a prober to first test locations on a wafer in a first prober-movement pattern specified in a first map; and

prior to completion of the first prober-movement pattern, moving the prober in a second prober-movement pattern specified in a second map.

32. The method of claim 31, wherein the first prober-movement pattern comprises a serpentine prober-movement pattern.

33. The method of claim 31, wherein the first prober-movement pattern comprises a row-by-row prober movement pattern.

34. The method of claim 31, wherein the first prober-movement pattern comprises a user-defined prober movement pattern.

35. A method comprising:

moving a prober to first test locations on a wafer in a first prober-movement pattern specified in a first map; and

upon completion of the first prober-movement pattern, moving the prober in a second prober-movement pattern specified in a second map.

36. A signal-bearing medium encoded with a data structure, wherein the data structure comprises:

an aggregate multiple wafer map including a prober movement map for probing a wafer comprising a mathematical union of a plurality of ordered map sets, wherein each of the map sets comprises at least one ordered site set, wherein each of the site sets comprises at least one ordered subsite set, wherein each of the subsite sets comprises at least one ordered measurement, and wherein a parametric test control system is to test a wafer using the mathematical union of the plurality of ordered map sets and wherein a statistical control limit of the parametric test control system causes a prober step sequence of the at least one ordered measurement to alternate.

37. The signal-bearing medium of claim 36, wherein the ordered measurement further comprises a key-value pair comprising a register key and an electrical test result value, and wherein the parametric test control system is to store a test measurement from the wafer in the electrical test result value.

38. The signal-bearing medium encoded with a data structure, wherein the data structure comprises:

a composite multiple wafer map including a prober movement map for probing a wafer comprising a mathematical intersection of a plurality of ordered map sets, wherein each of the map sets comprises at least one ordered site set, wherein each of the site sets comprises at least one ordered subsite set, and wherein each of the subsite sets comprises at least one ordered measurement, and wherein a parametric test control system is to test a wafer using the mathematical intersection of the plurality of ordered map sets and wherein a statistical control limit of the parametric test control system causes a probe step sequence of the at least one ordered measurement to alternate.

39. The signal-bearing medium of claim 38, wherein the ordered measurement further comprises a key-value pair comprising a register key and an electrical test result value, and wherein the parametric test control system is to store a test measurement from the wafer in the electrical test result value.

40. An apparatus comprising:

a parametric test control system to form the intersection of a plurality of prober-movement map sets and test a wafer using the intersection; and

a threshold parametric test to switch from a first prober-movement map to a second prober movement map of the plurality of prober-movement maps.

41. The apparatus of claim 40, wherein the intersection defines one contiguous probe stepping sequence for the wafer.

42. The apparatus of claim 40, wherein each of the plurality of map sets further comprises at least one ordered site set, wherein each of the site sets comprises at least one ordered subsite set, and wherein each of the subsite sets comprises at least one ordered measurement.

43. The apparatus of claim 42, wherein the ordered measurement further comprises a key-value pair comprising a register key and an electrical test result value, and wherein the parametric test control system is to store a test measurement from the wafer in the electrical test result value.

44. A semiconductor parametric test system, comprising:

a parametric test control system to form the union of a plurality of prober-movement map sets and to test a wafer using the union by switching to a second prober-movement map if a defect threshold was exceeded.

45. The semiconductor parametric test system of claim 44, wherein the parametric test control system further comprises a transition function to switch to a new map set.

46. The semiconductor parametric test system of claim 44, wherein the parametric test control system further comprises a transition function to invalidate previously visited map loops.

47. An apparatus comprising:

a prober;

a load-unload system;

an auto-alignment system; and

a test control system to instruct the load-unload system to load a wafer on a chuck, instruct the auto-alignment system to align the wafer, read a test plan, instruct the prober to probe the wafer based on a current probe map of the test plan, and to determine whether to select a new wafer map based on an error threshold of the current probe map.

48. The apparatus of claim 47, wherein the test control system is further to instruct the prober to move the wafer to a test location.

49. A method, comprising:

reading a first wafer map of test probe movements;

loading a wafer on a chuck;

performing tests on the wafer based on the test probe movements of the first wafer map; and

determining whether to switch to a second wafer map of test probe movements based on the first wafer map and results of the tests.

50. The method of claim 49, further comprising:

moving a test location on the wafer specified by the first wafer map to test pins.

51. The method of claim 49, further comprising:

moving a test location on the wafer specified by the second wafer map to test pins.

52. The method of claim 49, further comprising:

moving a prober in a serpentine pattern specified by the first wafer map.

53. The method of claim 49, further comprising:

moving a prober in a row-by-row pattern specified by the first wafer map.

54. The method of claim 49, further comprising:

moving a prober in a user-defined pattern specified by the second wafer map.

55. The method of claim 49, wherein determining whether to switch further comprises determining whether the results of the tests indicate that an error threshold has been exceeded.

56. The method of claim 49, wherein determining whether to switch further comprises determining whether the results of the tests indicate that a criteria has been met.

57. A method, comprising:

reading a first wafer map;

loading a wafer on a chuck;

performing tests on the wafer based on the first wafer map; and

determining whether to switch to a second wafer map based on the first wafer map and results of the tests; and

wherein determining whether to switch further comprises determining whether the results of the tests indicate that a badsite threshold has been exceeded.

58. The method of claim 57, further comprising:

determining the badsite threshold based on a total number of bad sites for the first wafer map and a total number of sites on the first wafer map.

59. A method, comprising:

reading a first wafer map;

loading a wafer on a chuck;

performing tests on the wafer based on the first wafer map; and

determining whether to switch to a second wafer map based on the first wafer map and results of the tests; and

wherein determining whether to switch further comprises determining whether the results of the tests indicate that a badwafer threshold has been exceeded.

60. The method of claim 59, further comprising:

determining the badwafer threshold based on a total number of bad wafers in a lot run and a total number of wafers.

61. A parametric test system comprising:

a loader to load a wafer;

a prober comprising test pins to perform tests on the wafer; and

a test control system to command the prober to move in a plurality of probing sequences specified in a respective plurality of maps and to switch between the maps based on measured results of the tests.

62. The parametric test system of claim 61, wherein the plurality of maps further comprise a truth table.

63. The parametric test system of claim 61, wherein the plurality of maps further comprise encode functions, decode functions, and look up functions.

64. The parametric test system of claim 61, wherein the test control system is further to command the prober to switch between the maps prior to completion of one of the plurality of probing sequences.

65. The parametric test system of claim 61, wherein the test control system is further to command the prober to switch between the maps prior to completion of one of the plurality of probing sequences based on error thresholds in the tests.

66. The parametric test system of claim 61, wherein the test control system is further to command the prober to remove electrical stimuli from the wafer prior to the switch between the maps.

67. The parametric test system of claim 61, wherein the test control system is further to command the prober to switch between the maps upon completion of one of the plurality of probing sequences.

68. The parametric test system of claim 61, wherein the test control system is further to command the prober to switch between the maps upon completion of one of the plurality of probing sequences based on error thresholds in the tests.

69. The parametric test system of claim 67, wherein the test control system is further to command the prober to remove electrical stimuli from the wafer prior to the switch between the maps.

70. The parametric test system of claim 61, wherein the test control system is further to switch from a composite wafer map to an aggregate wafer map.

71. The parametric test system of claim 61, wherein the test control system is further to switch from an aggregate wafer map to a composite wafer map.