Correlating high-speed serial interface data and FIFO status signals in programmable logic devices

• US 7,162,553 B1
• Filed: 10/01/2004
• Issued: 01/09/2007
• Est. Priority Date: 10/01/2004
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Xue, Ning, Lee, Chong H
• Primary Examiner(s): Tan; Vibol
• Application Number:
  US10/956,684
• Time in Patent Office: 830 Days
• Field of Search: 326/41, 326/86, 710/71
• US Class Current: 710/71
• CPC Class Codes: H03G 1/0088 using discontinuously variable devices, e.g. switch-operated
• CPC Class Codes: H03G 1/0094 using switched capacitors

Abstract

Status signals that are generated by one or more FIFO buffers in a high-speed serial interface (“HSSI”) may be combined with transmitted data samples in order to correlate the status signals to the respective data samples. The combined data and status signals may be transmitted either to the subsequent stages of the HSSI datapath or directly to the PLD via a dedicated path with less latency. The combined data and status signals can be used to determine whether a data sample corresponds to a valid data sample or an idle sequence, thereby allowing a user to control the flow of data.

Claims

1. A programmable logic device comprising:

programmable logic device core circuitry; and

high speed serial interface circuitry comprising receiver circuitry operative to receive and convert high speed serial data signals to a plurality of parallel data signals suitable for application to the programmable logic device core circuitry, and having at least one first-in first-out (FIFO) buffer operative to receive a data signal, to generate at least one status signal indicative of the amount of data in the at least one FIFO buffer, to combine the status signal with the corresponding data signal, and to send the combined status signal and data signal to at least one subsequent stage of the high speed serial interface datapath or to the programmable logic device core circuitry.

2. The programmable logic device of claim 1 wherein the at least one FIFO buffer is operative to combine the status signal with the corresponding data signal by adding the status signal to the beginning of the corresponding data signal.

3. The programmable logic device of claim 1 wherein the at least one FIFO buffer is operative to combine the status signal with the corresponding data signal by adding the status signal to the end of the corresponding data signal.

4. The programmable logic device of claim 1 wherein the receiver circuitry is configured to send the combined status signal and the corresponding data signal directly to the programmable logic device core circuitry upon generating the status signal.

5. The programmable logic device of claim 1 wherein the receiver circuitry is configured to send the combined status signal and the corresponding data signal to a subsequent processing stage in the receiver circuitry.

6. The programmable logic device of claim 1 wherein the status signal is indicative of whether the data signal corresponds to an idle character.

7. The programmable logic device of claim 6 wherein:

the corresponding data signal is not processed when the status signal indicates that the corresponding data signal is an idle character.

8. The programmable logic device of claim 1 wherein the at least one FIFO buffer is part of circuitry operative to receive the high speed serial data signals at a first frequency and to output the high speed serial data signals at a second frequency.

9. The programmable logic device of claim 1 wherein the at least one FIFO buffer is part of circuitry operative to align a plurality of channels of the high speed serial interface circuitry to a single frequency.

10. The programmable logic device of claim 1 wherein the at least one FIFO buffer generates the status signal when the amount of data in the FIFO buffer falls within a predetermined range.

11. The programmable logic device of claim 10 wherein the predetermined range is configurable.

12. The programmable logic device of claim 1 wherein the at least one FIFO buffer generates a plurality of status signals that each corresponds to a different predetermined range.

13. The programmable logic device of claim 1 wherein the high speed serial interface circuitry further comprises transmitter circuitry operative to receive and convert parallel data signals to high speed serial data signals suitable for application to an external device, and having at least one second FIFO buffer operative to receive a second data signal, to generate at least one second status signal indicative of the amount of data in the second FIFO buffer, and to combine the second status signal with the corresponding second data signal for output.

14. A digital signal processing system comprising:

processing circuitry;

a memory coupled to the processing circuitry; and

a device as defined in claim 1 coupled to the processing circuitry and the memory.

15. A printed circuit board on which is mounted a device as defined in claim 1.

16. The printed circuit board defined in claim 15 further comprising:

a memory mounted on the printed circuit board and coupled to the device.

17. The printed circuit board defined in claim 15 further comprising:

processing circuitry mounted on the printed circuit board and coupled to the device.

18. An integrated circuit device comprising:

high speed serial interface circuitry comprising receiver circuitry operative to receive and convert high speed serial data signals to a plurality of parallel data signals suitable for application to the integrated circuit device, and having at least one first-in first-out (FIFO) buffer operative to receive a data signal, to generate at least one status signal indicative of the amount of data in the at least one FIFO buffer, to combine the status signal with the corresponding data signal, and to send the combined status signal and data signal to at least one subsequent stage of the high speed serial interface datapath.

19. A method for correlating high speed serial interface data signals with first-in first-out (FIFO) status signals in a programmable logic device comprising:

receiving a data signal;

storing the data signal in at least one FIFO buffer;

generating at least one status signal indicative of the amount of data in the at least one FIFO buffer;

combining the status signal with the corresponding data signal; and

sending the combined status signal and data signal to at least one subsequent stage of the high speed serial interface datapath or to the programmable logic device core circuitry.

20. The method of claim 19 wherein combining the status signal with the corresponding data signal comprises adding the status signal to the beginning of the corresponding data signal.

21. The method of claim 19 wherein combining the status signal with the corresponding data signal comprises adding the status signal to the end of the corresponding data signal.

22. The method of claim 19 further comprising sending the combined status signal and corresponding data signal directly to programmable logic device core circuitry upon generating the status signal.

23. The method of claim 19 further comprising sending the combined status signal and corresponding data signal to a subsequent processing stage in the high speed serial interface circuitry.

24. The method of claim 19 wherein the status signal is indicative of whether the data signal corresponds to an idle character.

25. The method of claim 24 further comprising stopping the processing of the data signal when the status signal indicates that the corresponding data signal is an idle character.

26. The method of claim 19 further comprising:

receiving the data signal at a first frequency; and

sending as output the data signal at a second frequency.

27. The method of claim 19 further comprising aligning the data signal in each of a plurality of channels in the programmable logic device to a single frequency.

28. The method of claim 19 further comprising generating the status signal when the amount of data in the at least one FIFO buffer falls within a predetermined range.

29. The method of claim 28 further comprising generating a plurality of status signals that each corresponds to a different predetermined range.

30. The method of claim 28 wherein the predetermined range is configurable.

31. A method for processing a data sample having a high speed serial interface data signal and a corresponding status signal indicative of the amount of data in a first-in first-out (FIFO) buffer in a programmable logic device comprising:

receiving a data sample having a high speed serial interface data signal and a corresponding status signal;

determining whether the high speed serial interface data signal corresponds to an idle character based on the status signal;

processing the high speed serial interface data signal when the status signal indicates that the high speed serial interface data signal does not correspond to the idle character; and

stopping the processing of the high speed serial interface data signal when the status signal indicates that the high speed serial interface data signal corresponds to the idle character.

32. The method of claim 31 wherein the status signal is indicative of the amount of data in the FIFO buffer.