Memory hub and method for memory sequencing
First Claim
Patent Images
1. A memory module, comprising:
- a plurality of memory devices; and
a memory hub, comprising;
a link interface receiving memory requests for access to memory cells in at least one of the memory devices;
a memory device interface coupled to the memory devices, the memory device interface being operable to couple memory requests to the memory devices for access to memory cells in at least one of the memory devices and to receive read data responsive to at least some of the memory requests;
a performance counter coupled to the memory device interface, the performance counter operable to track at least one performance metric; and
a memory sequencer coupled to the link interface and the memory device interface, the memory sequencer being operable to couple memory requests to the memory device interface responsive to memory requests received from the link interface, the memory sequencer further being operable to dynamically adjust operability responsive to the performance metric tracked by the performance counter.
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Abstract
A memory module includes a memory hub coupled to several memory devices. The memory hub includes at least one performance counter that tracks one or more system metrics—for example, page hit rate, prefetch hits, and/or cache hit rate. The performance counter communicates with a memory sequencer that adjusts its operation based on the system metrics tracked by the performance counter.
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Citations
38 Claims
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1. A memory module, comprising:
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a plurality of memory devices; and a memory hub, comprising; a link interface receiving memory requests for access to memory cells in at least one of the memory devices; a memory device interface coupled to the memory devices, the memory device interface being operable to couple memory requests to the memory devices for access to memory cells in at least one of the memory devices and to receive read data responsive to at least some of the memory requests; a performance counter coupled to the memory device interface, the performance counter operable to track at least one performance metric; and a memory sequencer coupled to the link interface and the memory device interface, the memory sequencer being operable to couple memory requests to the memory device interface responsive to memory requests received from the link interface, the memory sequencer further being operable to dynamically adjust operability responsive to the performance metric tracked by the performance counter. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A memory hub, comprising:
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a link interface receiving memory requests for access to memory cells in at least one of the memory devices; a memory device interface coupled to the memory devices, the memory device interface being operable to couple memory requests to the memory devices for access to memory cells in at least one of the memory devices and to receive read data responsive to at least some of the memory requests; a performance counter coupled to the memory device interface, the performance counter operable to track at least one performance metric; and a memory sequencer coupled to the link interface and the memory device interface, the memory sequencer being operable to couple memory requests to the memory device interface responsive to memory requests received from the link interface, the memory sequencer further being operable to dynamically adjust operability responsive to the performance metric tracked by the performance counter. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17)
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18. A computer system, comprising:
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a central processing unit (“
CPU”
);a system controller coupled to the CPU, the system controller having an input port and an output port; an input device coupled to the CPU through the system controller; an output device coupled to the CPU through the system controller; a storage device coupled to the CPU through the system controller; a plurality of memory modules, each of the memory modules comprising; a plurality of memory devices; and a memory hub, comprising; a link interface receiving memory requests for access to memory cells in at least one of the memory devices; a memory device interface coupled to the memory devices, the memory device interface being operable to couple memory requests to the memory devices for access to memory cells in at least one of the memory devices and to receive read data responsive to at least some of the memory requests; a performance counter coupled to the memory device interface, the performance counter operable to track at least one performance metric; and a memory sequencer coupled to the link interface and the memory device interface, the memory sequencer being operable to couple memory requests to the memory device interface responsive to memory requests received from the link interface, the memory sequencer further being operable to dynamically adjust operability responsive to the performance metric tracked by the performance counter. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25, 26)
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27. A method of reading data from a memory module, comprising:
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receiving memory requests for access to a memory device mounted on the memory module; coupling the memory requests to the memory device responsive to the received memory request, at least some of the memory requests being memory requests to read data; receiving read data responsive to the read memory requests; tracking at least one performance metric; and adjusting operability of a memory sequencer based on the tracked performance metric. - View Dependent Claims (28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38)
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Specification