Multi-level memory cell
First Claim
1. A multi-level memory cell, comprising:
- a substrate;
a gate disposed over the substrate;
a source region and a drain region configured in the substrate on each side of the gate;
a tunneling dielectric layer disposed between the gate and the substrate;
a charge-trapping layer disposed between the tunneling dielectric layer and the gate; and
a top dielectric layer disposed between the charge-trapping layer and the gate, wherein the top dielectric layer has at least two portions from the source region to the drain region, and the portions adjacent to the source region has a different thickness to that of the portion adjacent to the drain region, and wherein the tunneling dielectric layer has substantially a same thickness from the source region to the drain region.
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Accused Products
Abstract
A multi-level memory cell including a substrate, a tunneling dielectric layer, a charge-trapping layer, a top dielectric layer, a gate and a pair of source/drain regions is provided. The tunneling dielectric layer, the charge-trapping layer and the top dielectric layer are sequentially formed between the substrate and the gate. The top dielectric layer has at least two portions, and the top dielectric layer in each portion has a different thickness. The source/drain regions are disposed in the substrate on each side of the gate. Since the thickness of the top dielectric layer in each portion is different, the electric field strength between the gate and the substrate when a voltage is applied to the memory cell are different in each portion. With the number of charges trapped within the charge-trapping layer different in each portion, a multiple of data bits can be stored within each memory cell.
37 Citations
9 Claims
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1. A multi-level memory cell, comprising:
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a substrate; a gate disposed over the substrate; a source region and a drain region configured in the substrate on each side of the gate; a tunneling dielectric layer disposed between the gate and the substrate; a charge-trapping layer disposed between the tunneling dielectric layer and the gate; and a top dielectric layer disposed between the charge-trapping layer and the gate, wherein the top dielectric layer has at least two portions from the source region to the drain region, and the portions adjacent to the source region has a different thickness to that of the portion adjacent to the drain region, and wherein the tunneling dielectric layer has substantially a same thickness from the source region to the drain region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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Specification
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- Resources
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Current AssigneePowerchip Semiconductor Manufacturing Corp. (Powerchip Technology Corporation)
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Original AssigneePowerchip Semiconductor Corporation (Powerchip Technology Corporation)
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InventorsHuang, Chiu-Tsung, Chang, Ko-Hsing
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Primary Examiner(s)Soward; Ida M.
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Application NumberUS10/707,677Publication NumberTime in Patent Office1,110 DaysField of Search257/314, 257/321, 257324-325, 257/333, 257/411, 257/638, 257/395, 257405-406US Class Current257/406CPC Class CodesH01L 29/40117 the electrodes comprising a...H01L 29/66833 with a charge trapping gate...H01L 29/7923 Programmable transistors wi...
