Method and apparatus for generating texture

• US 7,164,426 B1
• Filed: 11/28/2000
• Issued: 01/16/2007
• Est. Priority Date: 08/20/1998
• Status: Expired due to Term

• Current Assignee: Apple Inc.
• Original Assignee: Apple Computer Incorporated (Apple Inc.)
• Inventors: Hong, Bo, Duluk, Jerome F. Jr., Rashid, Abbas, Mammen, Abraham, Grass, Joseph P., Hessel, Richard E.
• Primary Examiner(s): Tung; Kee M.
• Assistant Examiner(s): Nguyen; Hau H.
• Application Number:
  US09/724,663
• Time in Patent Office: 2,240 Days
• Field of Search: 345/509, 345/516, 345564-566, 345/552, 345/558, 345/582, 711202-210
• US Class Current: 345/564
• CPC Class Codes: G06T 1/60 Memory management
• CPC Class Codes: G06T 11/001 Texturing; Colouring; Generation of texture or colour inpainting G06T5/77
• CPC Class Codes: G06T 11/40 Filling a planar surface by adding surface attributes, e.g. colour or texture
• CPC Class Codes: G06T 15/005 General purpose rendering architectures
• CPC Class Codes: G06T 15/04 Texture mapping
• CPC Class Codes: G06T 15/20 Perspective computation
• CPC Class Codes: G06T 15/30 Clipping
• CPC Class Codes: G06T 15/40 Hidden part removal
• CPC Class Codes: G06T 15/50 Lighting effects
• CPC Class Codes: G06T 15/80 Shading
• CPC Class Codes: G06T 15/83 Phong shading
• CPC Class Codes: G06T 15/87 Gouraud shading

Abstract

A deferred graphics pipeline processor comprising a texture unit and a texture memory associated with the texture unit. The texture unit applies texture maps stored in the texture memory, to pixel fragments. The textures are MIP-mapped and comprise a series of texture maps at different levels of detail, each map representing the appearance of the texture at a given distance from an eye point. The texture unit performs tri-linear interpolation from the texture maps to produce a texture value for a given pixel fragment that approximates the correct level of detail. The texture memory has texture data stored and accessed in a manner which reduces memory access conflicts and thus improves throughput of said texture unit.

Claims

1. An address reordering device for use in a memory system, the device comprising:

(1) a memory control block receiving dispatched addresses and sequentially performing read operations on the memory system using the dispatched addresses;

(2) a first level reorder queue storing a plurality of current addresses, each of the current addresses being equal to one of the dispatched addresses;

(3) a conflict queue storing stalled addresses, each of the stalled addresses being an address into texture memory that has its corresponding read operation postponed due to an address conflict;

(4) an in-order tag queue storing first tag information, each piece of first tag information corresponding to an address in the first level reorder queue;

(5) an out-of-order tag queue storing second tag information, each piece of second tag information corresponding to an address in the conflict queue;

(6) a conflict detection block comprising;

(6a) logic receiving a new address into texture memory, the new address being part of the sequence of addresses being received in a specific order;

(6b) logic detecting a memory conflict between the new address and any of the plurality of current addresses;

(6c) logic dispatching the new address to the memory control block if the conflict was not detected so as to make the new address into one of the dispatched addresses;

(6d) logic writing the new address into the first level reorder queue if the conflict is not detected so as to make the new address into one of the current addresses;

(6e) logic writing the new address into the conflict queue if the conflict is detected so as to make the new address into one of the stalled addresses;

(6f) logic writing new tag information corresponding to the new address into the in-order tag queue if the conflict is not detected;

(6g) logic writing the new tag information corresponding to the new address into the out-of-order tag queue if the conflict is detected; and

(6h) logic determining when the stalled addresses are dispatched to the memory control block; and

(7) logic reassembling data read from the memory system into the specific order, the reassembling being done according to the first tag information and the second tag information.

2. An address reordering method for use in a memory system, the method comprising the steps:

maintaining a list of current addresses, each of the current addresses being an address into a memory system that has been dispatched to the texture memory as part of a memory read operation that has not yet completed;

maintaining a list of stalled addresses, each of the stalled addresses being an address into the memory system that has its corresponding read operation postponed due to an address conflict;

maintaining a list of first tag information, each piece of first tag information corresponding to an address in the list of current addresses;

maintaining a list of second tag information, each piece of second tag information corresponding to an address in the list of stalled addresses;

receiving a new address into texture memory, the new address being part of a sequence of addresses being received in a specific order;

detecting the presence of a memory conflict between the new address and any of the current addresses;

if the conflict is not detected, dispatching the new address to perform a read operation from the texture memory;

if the conflict is not detected, adding the new address to the list of current;

if the conflict is detected, adding the new address to the list of stalled addresses;

if the conflict is not detected, adding the new tag information corresponding to the new address to the list of first tag information;

if the conflict is detected, adding the new tag information corresponding to the new address to the list of second tag information;

determining when the stalled addresses are dispatched to the memory control block; and

reassembling data read from the memory system into the specific order, the reassembling being done according to the first tag information and the second tag information.

3. The method of claim 2, the method further comprising the step:

performing a programmable mapping function of the bits within the dispatched address to (1) device bits selecting one or more memory devices from a plurality of memory devices; and

(2) bank bits selecting a memory bank within the selected memory device.

4. An address reordering device for use in a memory system, the device comprising:

a memory control block receiving dispatched addresses and sequentially performing read operations on the memory system using the dispatched addresses;

a first level reorder queue storing a plurality of current addresses, each of the current addresses being equal to one of the dispatched addresses;

a conflict queue storing stalled addresses, each of the stalled addresses being an address into texture memory that has its corresponding read operation postponed due to an address conflict;

an in-order tag queue storing first tag information, each piece of first tag information corresponding to an address in the first level reorder queue;

an out-of-order tag queue storing second tag information, each piece of second tag information corresponding to an address in the conflict queue;

a conflict detection and control logic unit; and

a reassembly logic unit reassembling data read from the memory system into the specific order, the reassembling being done according to the first tag information and the second tag information.