Tap time division multiplexing

• US 7,165,199 B2
• Filed: 12/17/2004
• Issued: 01/16/2007
• Est. Priority Date: 12/17/2003
• Status: Active Grant

• Current Assignee: STMicroelectronics Limited (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Limited (STMicroelectronics NV)
• Inventors: Warren, Robert
• Primary Examiner(s): Ton; David
• Application Number:
  US11/015,330
• Publication Number:
  US 20050172193A1
• Time in Patent Office: 760 Days
• Field of Search: 712/38, 710/52, 324/534, 714/27, 714/724, 714/701, 365/233
• US Class Current: 714/724
• CPC Class Codes: G01R 31/318536 Scan chain arrangements, e.g. connections, test bus, analog signals
• CPC Class Codes: G01R 31/318563 Multiple simultaneous testing of subparts

Abstract

An integrated circuit comprising (i) a plurality of portions, each portion including test control circuitry; and (ii) at least one test input arranged to receive test data, wherein the test data is clocked in a plurality of time slots, with test data for different ones of the plurality of portions being allocated to different time slots.

Claims

1. An integrated circuit comprising:

a plurality of portions, each portion including test control circuitry;

at least one test input arranged to receive test data;

wherein said test data is clocked in a plurality of time slots, with test data for different ones of said plurality of portions being allocated to different time slots.

2. A circuit as claimed in claim 1, wherein each time slot corresponds to a clock cycle.

3. A circuit as claimed in claim 2, wherein each time slot is divided into two half slots.

4. A circuit as claimed in claim 3, wherein each half slot of a time slot is allocated to a different one of said plurality of portions.

5. A circuit as claimed in claim 4, wherein frames are provided each contain n time slots.

6. A circuit as claimed in claim 5, wherein n is 8.

7. A circuit as claimed in claim 6, wherein the slots in a frame are allocated to predetermined ones of said plurality of portions of circuitry and said allocation is used for a plurality of said frames.

8. A circuit as claimed in claim 7, wherein one of said portions of circuitry is allocated to one half of the available slots.

9. A circuit as claimed in claim 8, wherein a given time slot is allocated to a given channel until information is received token to allocated the time slot to a different channel.

10. A circuit as claimed in claim 9, wherein the data amount per channel is equal to at least one slot.

11. A circuit as claimed in claim 6, wherein the slots are allocated dynamically.

12. A circuit as claimed in claim 11, wherein one of said portions of said circuitry is allocated to a quarter of the available slots.

13. An integrated circuit comprising:

a plurality of portions, each portion including test control circuitry; and

a plurality of test inputs arranged to receive test data, wherein in one mode of testing, data is transferred using tokens, with each token comprising m bits, m/2 bits being transferred on a rising edge of a clock signal and m/2 bits being transferred on a falling edge of a clock signal so that a token is transferred in a clock cycle.

14. A circuit as claimed in claim 13, wherein said token input is encoded.

15. A circuit as claimed in claim 14, wherein the decoding of said input will be dependent on if a slot has been allocated to a channel or not.

16. A circuit as claimed in claim 15, wherein if the channel is not allocated to a given slot, a predetermined combination of inputs will allocate the given slot to a channel with said token.

17. A circuit as claimed in claim 16, wherein if the channel is allocated, the token will provide one of the following:

data for the allocated channel;

deallocate the slot;

provide an idle slot; and

provide a reset.

18. A circuit as claimed in any of claim 17, wherein a reset mode is triggered when a token provides a predetermined input.

19. A circuit as claimed in claim 18, wherein information provided by said token may be provided by one half of said token.

20. A circuit as claimed in claim 19, wherein the two halves of the token are the same in at least some modes of operation of the circuit.

21. A circuit as claimed in claim 20, wherein a reset mode is provided when one half of the token has all low values.

22. A circuit as claimed in claim 21, wherein the coding used when a slot is deallocated or allocated is the same, but the information provided will be determined by whether the slot is allocated or not.

23. An integrated circuit having a first mode and a second mode of data transfer, wherein in the first mode of data transfer the time taken for a test data input from external test circuitry to be received and corresponding test data to be output to said external test circuitry is less than a clock period of said external test circuitry and in a second mode of data transfer the time taken for a test data input from external test circuitry to be received and corresponding test data to be output to said external test circuitry is greater than a clock period of said external test circuitry, said integrated circuit comprising:

decoding means for decoding said test data input;

target circuitry for interacting with said decoded test data input; and

encoding means for encoding a signal from said target circuitry for said external test circuitry, wherein said circuit is arranged in both said first and second mode of data transfer to have a n cycle operation in which said decoding means decodes said signal, said target circuitry interacts which said signal and said encoding means encodes said signal.

24. A circuit as claimed in claim 23, wherein n is 3.

25. Test circuitry for testing an integrated circuit, said test circuitry being external to said integrated circuit, said integrated circuit having a first mode and a second mode of data transfer, wherein in the first mode of data transfer the time taken for test data input from said external test circuitry to be received and corresponding test data to be output to said external test circuitry is less than a clock period of said external test circuitry and in a second mode of data transfer the time taken for a test data input from external test circuitry to be received and corresponding test data to be output to said external test circuitry is greater than a clock period of said external test circuitry, said test circuitry having a plurality of buffer locations for buffering signals received from and/or sent to said test circuitry, wherein with the first mode of data transfer, the signals received from and/or sent to the test circuitry have a lower delay provided by said buffer locations than with the second mode of data transfer.

26. Test circuitry as claimed in claim 25, wherein with the first mode of data transfer at least one of said buffer locations are bypassed.