Context selection and activation mechanism for activating one of a group of inactive contexts in a processor core for servicing interrupts

• US 7,165,257 B2
• Filed: 08/10/2001
• Issued: 01/16/2007
• Est. Priority Date: 02/08/2000
• Status: Expired due to Term

• Current Assignee: ARM Finance Overseas Limited (SoftBank Group Corp.)
• Original Assignee: MIPS Technologies Incorporated (Wave Computing, Inc.)
• Inventors: Melvin, Stephen, Musoll, Enrique, Nemirovsky, Mario
• Primary Examiner(s): Banankhah, Majid
• Assistant Examiner(s): SURYAWANSHI, SURESH
• Application Number:
  US09/927,129
• Publication Number:
  US 20020018486A1
• Time in Patent Office: 1,985 Days
• Field of Search: 370230-232, 370/392, 370422-430, 709/249, 709/224, 718100-108, 710/19, 712/229
• US Class Current: 718/108
• CPC Class Codes: G06F 9/461 Saving or restoring of program or task context
• CPC Class Codes: G06F 9/4812 by interrupt, e.g. masked
• CPC Class Codes: G06F 9/546 Message passing systems or structures, e.g. queues
• CPC Class Codes: H04L 47/2441 relying on flow classification, e.g. using integrated services [IntServ]
• CPC Class Codes: H04L 47/32 by discarding or delaying data units, e.g. packets or frames
• CPC Class Codes: H04L 47/621 Individual queue per connection or flow, e.g. per VC
• CPC Class Codes: H04L 47/6215 Individual queue per QOS, rate or priority
• CPC Class Codes: H04L 49/201 Multicast operation; Broadcast operation
• CPC Class Codes: H04L 49/205 Quality of Service based
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers
• CPC Class Codes: H04L 49/9073 Early interruption upon arrival of a fraction of a packet

Abstract

A logic system in a data packet processor is provided for selecting and releasing one of a plurality of contexts. The selected and released context is dedicated for enabling the processing of interrupt service routines corresponding to interrupts generated in data packet processing and pending for service. The system comprises, a first determination logic for determining control status of all of the contexts, a second determination logic for determining if a context is idle or not, a selection logic for selecting a context and a context release mechanism for releasing the selected context. Determination by the logic system that all contexts are singularly owned by an entity not responsible for packet processing and that at least one of the contexts is idle, triggers immediate selection and release of an idle one of the at least one idle contexts to an entity responsible for packet processing.

Claims

1. A logic system in a data packet processor for selecting and releasing a context among a plurality of such contexts, the selected and released context dedicated for enabling processing of interrupt service routines corresponding to interrupts generated in data packet processing and pending for service, the system comprising:

logic configured to;

determine control status of all of the contexts;

determine if a context is idle or not;

select a context; and

release the selected context;

wherein in response to determining that none of the plurality of contexts are owned by an entity responsible for packet processing (SPU) and that at least one of the contexts is idle, the logic is configured to trigger immediate selection and release of one of the at least one idle contexts to the entity responsible for packet processing upon determination that none of the contexts are owned by the entity responsible for packet processing and that there are no idle contexts, aborts pre-loading of a given context of the contexts to render the given context idle.

2. The logic system of claim 1 wherein the data packet processor is part of a data packet routing system.

3. The logic system of claim 2 wherein the data packet routing system is connected to a data packet network.

4. The logic system of claim 3 wherein the data packet network is the Internet network.

5. The logic system of claim 1 wherein the logic is integrated in a single hardware device.

6. The logic system of claim 5 wherein the hardware device is a register transfer unit.

7. The logic system of claim 1 further comprising a memory marker pointing to a memory address of a pre-defined instruction thread for invoking a stream to run in the released context.

8. The logic system of claim 1 wherein the selected and released context is dedicated to the servicing of pending interrupts.

9. The logic system of claim 7 wherein the memory containing the pre-defined thread is a cache memory used for containing program instructions.

10. The logic system of claim 7 wherein the memory containing the pre-defined thread is a dedicated memory section of a processing core, the core also containing the contexts.

11. The logic system of claim 1 wherein a priority scheme is used to select an idle context in the case of more than one idle context.

12. The logic system of claim 11 wherein the priority scheme comprises a prediction as to which of a plurality of idle contexts is likely to have access to needed functional units.

13. A method for selecting and releasing a context among a plurality of contexts to a processing entity for processing interrupt service routines associated with interrupts generated during data packet processing, the method comprising:

(a) determining that none of the plurality of contexts are under control of the processing entity;

(b) determining that there is at least one idle context within the plurality of contexts;

(c) selecting a first context of the at least one idle contexts for release; and

(d) releasing the first context to the processing entity, so the processing entity may process service routines and a memory marker is sent along with a release notification, the marker pointing to a location in memory where a pre-defined instruction thread exists to be used by the processing entity for invoking a stream to run in the released context.

14. The method of claim 13 further comprising a step (e) for processing low-priority tasks before releasing the selected context.

15. The method of claim 13 wherein the data packet processing is performed by a processor of a data packet router connected to a data packet network.

16. The method of claim 14 wherein the data packet network is the Internet network.

17. The method of claim 13 wherein in step (a) the determination of control status of the contexts is made by logic on a hardware device.

18. The method of claim 13 wherein in step (b) the determination of idle status of the contexts is made by logic on a hardware device.

19. The method of claim 13 wherein in steps (a) and (b) are enabled by a single hardware device containing the appropriate logics.

20. The method of claim 19 wherein in steps (c) and (d) are also enabled by the same hardware device containing the appropriate logics.

21. A method for processing service routines associated in a data packet processing system using a dedicated context selected among a plurality of contexts not under control of a data packet processor, the method comprising:

(a) receiving, at the processor, notification of a selected context about to be released and a memory marker pointing to an instruction thread in memory;

(b) fetching the instruction thread designated by the received marker;

(c) executing the instruction thread in the released context;

(d) detecting at least one pending interrupt that requires processing; and

(e) running the corresponding service routine or routines that satisfies the at least one interrupt.

22. The method of claim 21 further comprising a step for calling and executing other service routines after all interrupts are serviced.

23. The method of claim 21 wherein the data processing system is a data packet router connected to a data packet network.

24. The method of claim 23 wherein the data packet network is the Internet network.

25. The method of claim 21 wherein in step (a) the instruction thread has at least one instruction invoking a processing stream.

26. The method of claim 21 wherein in step (a) the memory marker is a program counter number of the beginning location of the thread in memory.

27. The method of claim 21 wherein in step (a) the memory is an instruction cache memory containing a program of instructions.

28. The method of claim 21 wherein in step (a) the memory is a dedicated memory in the processing core, the core also containing the contexts.

29. The method of claim 21 wherein in step (b) fetching the instruction thread occurs before the context is actually under the control of the processor.

30. The method of claim 21 wherein in step (c) the instruction thread contains at least one instruction invoking a stream.

31. The method of claim 30 wherein in step (c) the instruction thread further contains an instruction for checking for pending interrupts.

32. The method of claim 21 wherein in step (d) the interrupts are taken by priority in the event of more than one pending.

33. The method of claim 21 wherein steps (a) through (e) are completed when no other contexts are under control of the processor.