Erase verify for nonvolatile memory using reference current-to-voltage converters

• US 7,167,396 B2
• Filed: 08/05/2005
• Issued: 01/23/2007
• Est. Priority Date: 08/30/2001
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Chevallier, Christophe J.
• Primary Examiner(s): Tran; Andrew Q.
• Application Number:
  US11/198,200
• Publication Number:
  US 20050270838A1
• Time in Patent Office: 536 Days
• Field of Search: 365/185.22, 365/185.21, 365/185.2, 365/185.18, 365/185.03
• US Class Current: 365/185.22
• CPC Class Codes: G11C 16/3404 Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
• CPC Class Codes: G11C 16/344 Arrangements for verifying correct erasure or for detecting overerased cells

Abstract

A memory device verify system determines a state of memory cells in a memory. The memory includes a memory array having a plurality of memory cells coupled to bit lines. A verify circuit is coupled to the bit lines to determine if memory cells have a erase level that is within predetermined upper and lower limits. The verify circuit can include first and second comparators. In one embodiment, the first comparator is used to compare a bit line current with an upper first reference current. The second comparator is used to compare a bit line current with a lower second reference current. The comparator circuit is not limited to reference currents, but can use reference voltages to compare to a bit line voltage. The verify circuit, therefore, eliminates the need for separate bit line leakage testing to identify over-erased memory cells.

Claims

1. A non-volatile memory comprising:

an array of non-volatile memory cells arranged in columns using bit lines;

first and second comparators for comparing a bit line voltage with first and second reference voltages respectively to respectively produce first and second output signals;

a bit line current-to-voltage converter coupled between a selected one of the bit lines and the first and second comparators to generate the bit line voltage in response to a bit line current; and

first and second reference current-to-voltage converters, for respectively generating the first and second reference voltages, respectively coupled between the first and second comparators and first and second reference currents, each reference current-to-voltage converter comprising;

a resistor;

an activation circuit coupled to the resistor; and

a reference current source coupled to the activation circuit for generating a voltage drop across the resistor that provides one of the first or second reference voltages in response to the first or second reference currents respectively.

2. The non-volatile memory of claim 1 wherein the memory cells comprise a plurality of floating gate memory cells.

3. The non-volatile memory of claim 1 wherein each memory cell is comprised of a source region, a drain region, and a control gate.

4. The non-volatile memory of claim 3 wherein the control gate of each memory cell in a row of the array is coupled by a word line.

5. The non-volatile memory of claim 3 wherein the drain regions of each memory cell in a column are coupled by a common bit line.

6. The non-volatile memory of claim 3 wherein the source regions of each memory cell in a column are coupled by a common source line.

7. The non-volatile memory of claim 1 wherein the bit line current-to-voltage converter converts the bit line current to the bit line voltage that indicates a state of the memory cell.

8. A memory device comprising:

an array of non-volatile memory cells arranged in columns using bit lines that have a bit line current indicative of a state of a memory cell;

a bit line current-to-voltage converter coupled to a selected one of the bit lines for generating a bit line voltage in response to the bit line current;

first and second reference current-to-voltage converters, for respectively generating first and second reference voltages from first and second reference currents, each reference current-to-voltage converter comprising;

a resistor;

an activation transistor having a source coupled to the resistor;

an inverter circuit coupled between a gate and a drain of the activation transistor; and

a reference current source, coupled to the drain, for generating a voltage drop across the resistor that provides either a first or a second reference voltage in response to the first or second reference currents respectively;

first and second comparators for comparing the bit line voltage with the first and second reference voltages, respectively, to respectively produce first and second output signals; and

control circuitry to perform erase operations in response to the first and second output signals.

9. The device of claim 8 wherein the memory device is a flash memory device.

10. The device of claim 8 wherein if the first and second output signals indicate an over-erased cell, the control circuitry is adapted to perform a soft program operation.

11. The system of claim 8 wherein if the first and second control signals indicate an under-erased cell, the control circuitry is adapted to perform an additional erase operation.

12. The device of claim 8 wherein the memory cells comprise a plurality of floating gate memory cells.

13. A memory system comprising:

a processor for controlling the system; and

a memory device coupled to the processor and comprising;

an array of non-volatile memory cells arranged in columns using bit lines that have a bit line current indicative of a state of a memory cell;

a bit line current-to-voltage converter coupled to a selected one of the bit lines for generating a bit line voltage in response to the bit line current;

first and second reference current-to-voltage converters, for respectively generating first and second reference voltages from first and second reference currents, each reference current-to-voltage converter comprising;

a resistor;

an activation transistor having a source coupled to the resistor;

an inverter circuit coupled between a gate and a drain of the activation transistor; and

a reference current source, coupled to the drain, for generating a voltage drop across the resistor that provides either the first or the second reference voltage in response to the first or second reference currents respectively;

first and second comparators for comparing the bit line voltage with the first and second reference voltages, respectively, to respectively produce first and second output signals; and

control circuitry to perform erase operations in response to the first and second output signals.

14. The system of claim 13 wherein the control circuitry is coupled to control lines from the processor.

15. The system of claim 13 wherein the processor generates data and address lines for communicating with the memory device.

16. The system of claim 13 wherein the memory array is comprised of flash memory cells.