Semiconductor storage device and refresh control method therefor

• US 7,167,403 B2
• Filed: 01/26/2005
• Issued: 01/23/2007
• Est. Priority Date: 01/30/2004
• Status: Expired due to Fees

• Current Assignee: Longitude Semiconductor S.à r.l. (Vector Capital Corporation)
• Original Assignee: Elpida Memory Incorporated (Micron Technology, Inc.)
• Inventors: Riho, Yoshiro, Ito, Yutaka
• Primary Examiner(s): Nguyen; Tuan T.
• Application Number:
  US11/042,441
• Publication Number:
  US 20050169083A1
• Time in Patent Office: 727 Days
• Field of Search: 365/200, 365/222
• US Class Current: 365/200
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40615 Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
• CPC Class Codes: G11C 11/40626 Temperature related aspects of refresh operations
• CPC Class Codes: G11C 11/4072 Circuits for initialization, powering up or down, clearing memory or presetting
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2207/104 Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs
• CPC Class Codes: G11C 2211/4061 Calibration or ate or cycle tuning
• CPC Class Codes: G11C 2211/4062 Parity or ECC in refresh operations
• CPC Class Codes: G11C 2211/4067 Refresh in standby or low power modes
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory

Abstract

A dynamic semiconductor storage device in which the power supply current during the standby time is diminished to decrease the power consumption and to suppress the chip area from increasing. During the normal operation, the information as to a word line associated with a row address accessed during the normal operation is stored in a RAM. In entering self refresh, data of memory cells connected to a word line associated with a row address accessed during the normal operation time is read out and check bits for the data are appended in an encoder and written in a check bit area. As an initializing operation for the first self refresh entry after power up sequence, the data retention time of the memory cells is inspected every word line. Based on the results of inspection, the setting value of the refresh period of the word line is determined and written in the RAM to set the word line based refresh period. During error check for the refresh operation, any error is corrected by an error correction circuit.

Claims

1. A semiconductor storage device comprising:

a memory array including a plurality of memory cells, arrayed at points of intersection between a plurality of bit lines and a plurality of word lines, said memory cells being in need of refresh for retention of data;

a storage circuit for recording the word line information associated with a row address accessed during the operation in the normal mode;

an encoding circuit for generating, at the time of entry from a normal mode to a preset self refresh mode, error correcting codes for data of the memory cells connected to the word line associated with the row address accessed during the operation in the normal mode prior to the time of the entry to said self refresh mode, and for writing the so generated codes in a preset storage area;

an error detected circuit for detecting an error in the data of the memory cells connected to the word line selected by a refresh address; and

a decoding circuit for correcting the data of the memory cell where an error has been detected.

2. A semiconductor storage device according to claim 1, further comprising:

a circuit for managing control for changing the setting value of the refresh period for said word line connected to the memory cell where an error has been detected in said error detection circuit and for recording the setting value thus changed in said storage circuit designed to store the refresh period of said word line.

3. The semiconductor storage device according to claim 1, further comprising a self refresh control circuit including:

a circuit for generating a refresh address; and

a circuit for generating a refresh period;

said refresh period generating circuit variably controlling the length of said refresh period in refreshing with the preset refresh period, based on the result of error detection in said error detection circuit.

4. The semiconductor storage device according to claim 3, wherein the circuit for generating the refresh period shortens said refresh period in a preset proportion in case an error has been detected in said error detection circuit.

5. The semiconductor storage device according to claim 3, wherein the circuit for generating the refresh period lengthens said refresh period in a preset proportion in case no error has been detected in said error detection circuit.

6. The semiconductor storage device according to claim 1, wherein said error detection circuit includes a detection circuit for detecting a one-bit error every plural bit lines in said memory array.

7. The semiconductor storage device according to claim 6, further comprising:

a unit circuit including;

first and second switch devices having control terminals connected to one of paired bit lines arranged between said memory array and the sense amplifier and having one ends connected in common; and

third and fourth switch devices having control terminals connected to the other of paired bit lines and having one ends connected in common;

with the other ends of said first and third switches being cross-connected and with the other ends of said second and fourth switches being cross-connected;

one ends of said first and second switch devices on one side end of a plurality of paired bit lines being connected to a signal line for a check bit, one ends of said third and fourth switch devices being connected to a complementary line of said signal line for a check bit, the other ends of said first and third switches cross-connected being connected to one ends of said first and second switch devices of a neighboring unit circuit and the other ends of said second and fourth switches cross-connected being connected to one ends of said third and fourth switch devices of said neighboring unit circuit; and

wherein on the other side end of a plurality of paired bit lines, the other ends of said first and third switches cross-connected are connected to a check bit output line.

8. The semiconductor storage device according to claim 1, wherein said error detection circuit is provided in association with said memory cell array;

and

wherein a set of said encoding circuit and said decoding circuit is provided per a bank composed of a plurality of memory arrays.

9. The semiconductor storage device according to claim 8, wherein one bank has a plurality of memory arrays;

and

wherein said error detector, provided at a rate of one for each memory array, includes a detector for detecting one bit error every plural bit lines in said memory array.

10. The semiconductor storage device according to claim 1, wherein one bank includes a plurality of memory arrays and has a hierarchical word line configuration in which a sub-word line is provided every plural memory arrays for each main word line;

and wherein the information as to whether or not a row address has been accessed is recorded in said storage circuit every main word line.

11. The semiconductor storage device according to claim 9, wherein said error detector includes a circuit which, in case an error has been detected for a refresh period at the time of inspection of the refresh period for said sub-word line, updates the refresh period of said sub-word line to a refresh period of a shorter period than said refresh period and records the updated value as a setting value of a storage circuit configured for storing the refresh period of said sub-word line.

12. The semiconductor storage device according to claim 1, further comprising:

a row decoder for decoding a row address to select a world line; and

a random-access storage circuit including a row decoder for decoding a row address to select a word line and also including a cell selected in association with the word line selected by said row decoder;

wherein the information as to whether or not the row address has been accessed is written in and read out from a cell selected by a word line as selected by said row decoder.

13. A refresh controlling method for a semiconductor storage device including a memory array including a plurality of memory cells, arrayed at points of intersection between a plurality of bit lines and a plurality of word lines, said memory cells being in need of refresh for retention of data;

said method comprising the steps of;

recording the information as to the word line, associated with a row address accessed during the operation in the normal mode, in a storage circuit in association with said word line;

managing control for generating check bit information for data of memory cells connected to a word line associated with a row address accessed during the operating period with said normal mode at the time of entry from the normal mode to the self refresh mode and prior to entry to said self refresh mode, and writing the so generated check bit information in a check bit area added to said memory array; and

correcting data of the memory cell where an error has been detected.

14. A semiconductor storage device comprising:

a memory array including a plurality of memory cells, arrayed at points of intersection between a plurality of bit lines and a plurality of word lines, said memory cells being in need of refresh for retention of data;

an error detection circuit for detecting whether or not there is any error in data retained by said memory cell; and

a circuit for variably controlling the length of said refresh period based on the results of error detection in said error detection circuit in the refresh operation.

15. The semiconductor storage device according to claim 14, wherein said error detection circuit includes a detection circuit for detecting a one-bit error in association with a plurality of bit lines in said memory array.

16. The semiconductor storage device according to claim 14, further comprising:

a circuit for correcting an error in data of the memory cell where said error has been detected.

17. A refresh controlling method for a semiconductor storage device comprising a memory array including a plurality of memory cells, arrayed at points of intersection between a plurality of bit lines and a plurality of word lines, said memory cells being in need of refresh for retention of data;

said method comprising the steps of;

detecting whether or not there is any error in data retained by said memory cell, during a refresh operation; and

variably controlling the length of said refresh period based on the results of error detection in said error detection circuit.

18. The refresh controlling method for a semiconductor storage device according to claim 17, further comprising a step of

correcting an error in data of the memory cell where said error has been detected.