Analog N-tap FIR receiver equalizer

• US 7,167,517 B2
• Filed: 05/22/2001
• Issued: 01/23/2007
• Est. Priority Date: 05/22/2000
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Board of Trustees of the Leland Stanford Junior University (Stanford Management Co.)
• Inventors: Lee, Thomas H., Farjad-Rad, Ramin
• Primary Examiner(s): Ha; Dac V.
• Application Number:
  US09/863,081
• Publication Number:
  US 20010043649A1
• Time in Patent Office: 2,072 Days
• Field of Search: 375/229, 375232-234, 375/316, 375/350, 708/313, 708/819, 341/61
• US Class Current: 375/232
• CPC Class Codes: H03H 15/00 Transversal filters electromechanical filters H03H9/46, H03H9/70
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/14 for assuring constant frequency when supply or correction voltages fail or are interrupted
• CPC Class Codes: H04L 2025/03477 not time-recursive
• CPC Class Codes: H04L 25/0307 using blind adaptation

Abstract

An equalizer includes plural samplers for sampling an incoming input data stream according to plural phases of a sampling clock, each sampler producing a data sample. Operating in the analog domain, a multi-tap finite impulse response (FIR) filter weights the data samples and combines the weighted data samples to produce a filtered data bit. The filtered data bits thus form an equalized output data stream. The equalizer can compensate for characteristics of a communications channel, such as low-pass characteristics. The channel may carry high-speed, e.g., multi-gigabit per second, traffic.

Claims

1. A receiver equalizer, comprising:

samplers for sampling an incoming input data stream according to plural phases of a sampling clock, each sampler producing a demultiplexed data sample that changes at a slower rate than the incoming signal; and

a plurality of multi-tap finite impulse response (FIR) filters, where each FIR filter, in an analog domain, for each demultiplexed data sample, weights said demultiplexed data sample and at least one previous demultiplexed data sample, and combines said weighted data samples to produce an equalized demultiplexed data value, wherein each FIR filter includes at least one scaler, wherein each of the scalers has dedicated tap weight.

2. The equalizer of claim 1, wherein each of the plurality of multi-tap FIR filters comprises:

a first current source that produces a first current which is proportional to a product of a previous data sample and a weight associated with said previous data sample tap;

a second current source that produces a second current which is proportional to an instance data sample;

an adder circuit which subtracts the second current from the first current to produce a third current; and

a converter circuit which converts the third current to a voltage corresponding to the equalized data bit.

3. The equalizer of claim 1, wherein the equalizer compensates for characteristics of a communications channel.

4. The equalizer of claim 3, wherein the communications channel is a multi-gigabit per second link.

5. The equalizer of claim 3, wherein the communications channel is a cable.

6. The equalizer of claim 3, wherein the communications channel is a circuit board trace.

7. The equalizer of claim 3, wherein the communications channel is an optical fiber.

8. The equalizer of claim 3, wherein the communications channel has low-pass characteristics.

9. The equalizer of claim 1, wherein the FIR filter is a high-pass filter.

10. The equalizer of claim 1, further comprising:

second samplers for sampling and holding the equalized data bit values; and

sense amplifiers for converting the sampled equalized data bit values to digital values.

11. A method for equalizing an incoming input data stream, comprising:

sampling the input data stream according to plural phases of a sampling clock to produce demultiplexed data samples changing at a slower rate than the incoming signal; and

filtering the slow changing demultiplexed data samples with a plurality of analog multi-tap finite impulse response (FIR) filters, having dedicated tap weights, to produce demultiplexed equalized data values.

12. The method of claim 11, wherein filtering comprises:

in an analog domain, weighting the data samples; and

combining the weighted data samples to produce an equalized data bit.

13. The method of claim 12, wherein the FIR filter is a high-pass filter.

14. The method of claim 11, further comprising:

sampling and holding the equalized data bit values; and

converting the sampled equalized data bit values to digital values.

15. A receiver equalizer, comprising:

means for sampling the input data stream according to plural phases of a sampling clock to produce demultiplexed data samples changing at a lower rate than the incoming signal; and

means for filtering the slower rate demultiplexed data samples with a plurality of an analog multi-tap finite impulse response (FIR) filters to produce demultiplexed equalized data values;

means for sampling and holding the demultiplexed equalized data bit values; and

means for converting the sampled equalized data bit values to digital values.

16. A multi-tap analog finite impulse response filter, comprising:

at least one combined voltage-current converter and scaler that produces a first current from an input voltage which is proportional to a product of a previous data sample voltage and a weight associated with said previous data sample tap;

a voltage-current converter that produces a second current which is proportional to an instance data sample voltage;

an adder circuit which subtracts the second current from the first current to produce a third current; and

a converter circuit which converts the third current to a voltage corresponding to the equalized data voltage.

17. The multi-tap analog FIR filter of claim 16, where the combined voltage-current converter and scaler is implemented by modulating the relative strength for source current) of the voltage-current converter according to the weight associated with its input data sample.

18. The combined-voltage current converter and scaler of claim 17, where conversion and scaling is performed by an open-loop circuit.

19. A multi-tap analog finite impulse response filter method, comprising:

producing at least a first current from an input voltage which is proportional to a product of a previous data sample voltage and a weight associated with said previous data sample tap;

producing a second current which is proportional to an instance data sample voltage;

subtracting the second current from the first current to produce a third current; and

converting the third current to a voltage corresponding to the filtered data bit.

20. The multi-tap analog FIR filter of claim 19, where output product current is produced by modulating a current, which is proportional to the data sample voltage, according to the weights associated with that data sample tap.

21. A multi-tap analog finite impulse response filter, comprising:

means for producing at least a first current from an input voltage which is proportional to a product of a previous data sample voltage and a weight associated with said previous data sample tap;

means for producing a second current which is proportional to an instance data sample voltage;

means for subtracting the second current from the first current to produce a third current; and

means for converting the third current to a voltage corresponding to the filtered data bit.