Accessory control interface

• US 7,167,935 B2
• Filed: 03/10/2004
• Issued: 01/23/2007
• Est. Priority Date: 03/08/2002
• Status: Expired due to Term

• Current Assignee: Nokia Corporation
• Original Assignee: Nokia Corporation
• Inventors: Hellberg, Tino
• Primary Examiner(s): Dang; Khanh
• Application Number:
  US10/798,213
• Publication Number:
  US 20040250002A1
• Time in Patent Office: 1,049 Days
• Field of Search: None
• US Class Current: 710/58
• CPC Class Codes: G06F 1/1632 External expansion units, e.g. docking stations
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: H04M 1/72409 by interfacing with external accessories hands-free H04M1/60
• CPC Class Codes: H04M 2201/10 Logic circuits
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Disclosed is an interface (10, 40) between a master device (30) and a slave device (20). The interface includes a bit serial bidirectional signal line (10A) for conveying commands and associated data from the master device to the slave device, and for conveying a reset signal, an interrupt signal, and a learning sequence signal for specifying a duration of a bit time for data transferred from the slave device to the master device. The bit serial bidirectional signal line further indicates an accessory device connected/disconnected state to the master device.

Claims

1. An interface between a master device and a slave device, said interface comprising a serial data bidirectional signal line for conveying commands and associated data from said master device to said slave device, said serial data bidirectional signal line further conveying other signals, said other signals comprising a reset signal, an interrupt signal, and a learning sequence signal for specifying a duration of a bit time for data transferred from said slave device to said master device, where said interface comprises a resistance R coupled between the serial data bidirectional signal line and a circuit ground, and a pull up resistance R_PU installed in the master device, wherein R and R_PU together form a resistor voltage divider network.

2. An interface as in claim 1, where said master device is comprised of a personal digital assistant.

3. An interface as in claim 1, where said master device is comprised of a mobile terminal.

4. An interface as in claim 1, where said serial data bidirectional signal line further conveys a slave device connected/disconnected state to said master device.

5. An interface for coupling a slave device to a master device, said interface supporting a serial data bidirectional signal line that conveys commands and associated data from said master device to said slave device, said serial data bidirectional signal line further conveying other signals, said other signals comprising a reset signal, an interrupt signal, and a learning sequence signal for specifying a duration of a bit time for data transferred from said slave device to said master device, where said interface comprises, in said slave device, an Accessory Control Interface chip with an oscillator providing a clock signal to said Accessory Control Interface chip, where the bit time is a multiple of the clock signal, and where said master device adapts by sampling of the data transferred from said slave device in accordance with the specified duration of the bit time.

6. An interface as in claim 5, where said interface is disposed within said slave device and comprises an oscillator for generating a clock signal, where the bit time is a multiple of the clock signal period, and where said master device samples said serial data bidirectional signal line in accordance with the specified duration of the bit time.

7. An interface as in claim 5, where said interface is disposed within said slave device and comprises a non-volatile memory for storing slave device related feature data that is readable by said master device over said serial data bidirectional signal line in response to a read command sent from said master device to said interface over said serial data bidirectional signal line.

8. An interface as in claim 5, where said interface is disposed within said slave device and comprises a challenge/response authentication function that is challenged in response to an authentication challenge command and associated challenge data received from said master device over said serial data bidirectional signal line, and where authentication result data is sent to said master device over said serial data bidirectional signal line in response to receiving an authentication result command from said master device over said serial data bidirectional signal line.

9. An interface as in claim 5, where said serial data bidirectional signal line further conveys a slave device connected/disconnected state to said master device.

10. An interface as in claim 5, where said master device is comprised of a mobile terminal.

11. An interface as in claim 10, where said mobile terminal samples said serial data bidirectional signal line at a rate established by a mobile terminal sleep clock.

12. An interface as in claim 5, where said master device is comprised of a personal digital assistant.

13. An interface for coupling a slave device to a master device, said interface being disposed in said slave device and supporting a serial data bidirectional signal line that conveys commands and associated data from said master device to said slave device, said serial data bidirectional signal line further conveying other signals, said other signals comprising a reset signal, where said interface comprises, in said slave device, an Accessory Control Interface chip with an oscillator providing a clock signal to said Accessory Control Interface chip, where the bit time is a multiple of the clock signal, and where said master device adapts by sampling of the data transferred from said slave device in accordance with the specified duration of the bit time.

14. An interface as in claim 13, where said other signals further comprise an interrupt signal and a learning sequence signal for specifying a duration of a bit time for data transferred from said slave device to said master device.

15. An interface for coupling a slave device to a master device, said interface being disposed in said slave device and supporting a serial data bidirectional signal line that conveys commands and associated data from said master device to said slave device, said serial data bidirectional signal line further conveying other signals, said other signals comprising an interrupt signal, where said interface comprises, in said slave device, an Accessory Control Interface chip with an oscillator providing a clock signal to said Accessory Control Interface chip, where the bit time is a multiple of the clock signal, and where said master device adapts by sampling of the data transferred from said slave device in accordance with the specified duration of the bit time.

16. An interface as in claim 15, where said other signals further comprise a reset signal and a learning sequence signal for specifying a duration of a bit time for data transferred from said slave device to said master device.

17. An interface circuit for coupling a slave device to a master device, said interface being disposed in said slave device and supporting a serial data bidirectional signal line that conveys commands and associated data from said master device to said slave device, said serial data bidirectional signal line further conveying other signals, said other signals comprising a learning sequence signal for specifying a duration of a bit time for data transferred from said slave device to said master device, where said interface comprises, in said slave device, an Accessory Control Interface chip with an oscillator providing a clock signal to said Accessory Control Interface chip, where the bit time is a multiple of the clock signal, and where said master device adapts by sampling of the data transferred from said slave device in accordance with the specified duration of the bit time.

18. An interface as in claim 17, where said interface comprises an oscillator for generating a clock signal, where the duration of the bit time is a multiple of the clock signal period, and where said master device samples said serial data bidirectional signal line in accordance with the specified duration of the bit time.

19. An interface as in claim 18, where a logic zero and a logic one are distinguished by a presence or absence of a transition occurring on said serial data bidirectional signal line by a predetermined point in the specified duration of the bit time.

20. An interface as in claim 19, where the specified duration of the bit time is given by T, and where the predetermined point is about T/2.

21. An interface as in claim 17, where said interface comprises at least one register that is readable by said master device over said serial data bidirectional signal line.

22. An interface as in claim 17, where said interface comprises at least one register that is writable by said master device over said serial data bidirectional signal line.

23. An interface as in claim 17, where said interface comprises at least one memory device location that is readable by said master device over said serial data bidirectional signal line.

24. An interface as in claim 17, where said interface comprises at least one memory device location that is writable by said master device over said serial data bidirectional signal line.

25. An interface as in claim 17, where said interface comprises an authentication block that is addressable by commands sent by said master device over said serial data bidirectional signal line, and that responds to at least one command with response data sent to said master device over said serial data bidirectional signal line.

26. An interface as in claim 17, where said other signals further comprise a reset signal and an interrupt signal.

27. A master device comprising an interface for coupling to a slave device, the interface comprising a serial data bidirectional signal line;

wherein a reset signal is sent from the master device to the slave device over the serial data bidirectional signal line;

and a learning sequence signal is sent to the master device over the serial data bidirectional signal line for specifying a duration of a bit time for data transferred between the master device and the slave device;

wherein at least one of data and commands are communicated between the master device and the slave device over the serial data bidirectional signal line, and the interface comprises an Accessory Control Interface chip with an oscillator providing a clock signal to said Accessory Control Interface chip, where the bit time is a multiple of the clock signal, and where said master device adapts by sampling of the data transferred from said slave device in accordance with the specified duration of the bit time.

28. The master device as in claim 27, where the master device samples the serial data bidirectional signal line in accordance with the specified duration of the bit time.

29. The master device as in claim 28, where a logic zero and a logic one are distinguished by a presence or absence of a transition occurring on the serial data bidirectional signal line by a predetermined point in the specified duration of the bit time.

30. The master device as in claim 29, where the specified duration of the bit time is given by T, and where the predetermined point is about T/2.

31. The master device as in claim 27, where the master device includes a mobile terminal.

32. The master device as in claim 27, where the master device is selected from the group consisting of a cellular telephone, a personal computer, a personal organizer, a personal digital assistant, an email terminal, a laptop computer, a notebook computer, a workstation, and a home electronic device.

33. A slave device comprising:

an interface for coupling to a master device, the interface comprising a serial data bidirectional signal line;

wherein a reset signal is sent from the master device to the slave device over the serial data bidirectional signal line; and

a learning sequence signal is sent to the master device over the serial data bidirectional signal line for specifying a duration of a bit time for data transferred between the master device and the slave device;

wherein at least one of data and commands are communicated between the master device and the slave device over the serial data bidirectional signal line, and the interface comprises an Accessory Control Interface chip with an oscillator providing a clock signal to said Accessory Control Interface chip, where the bit time is a multiple of the clock signal, and where said master device adapts by sampling of the data transferred from said slave device in accordance with the specified duration of the bit time.

34. The slave device as in claim 33, comprising an accessory selected from the group consisting of a battery charger, a headset and a hands free adapter.

35. A master device for coupling to a slave device through an interface, the interface comprising a serial data bidirectional signal line for conveying commands and associated data from said master device to said slave device, said serial data bidirectional signal line further conveying other signals, said other signals comprising a reset signal, an interrupt signal, and a learning sequence signal for specifying a duration of a bit time for data transferred from said slave device to said master device, where said interface comprises a resistance R coupled between the serial data bidirectional signal line and a circuit ground, and a pull up resistance R_PU installed in the master device, wherein R and R_PU together form a resistor voltage divider network.

36. A slave device for coupling to a master device through an interface, the interface comprising a serial data bidirectional signal line for conveying commands and associated data from said master device to said slave device, said serial data bidirectional signal line further conveying other signals, said other signals comprising a reset signal, an interrupt signal, and a learning sequence signal for specifying a duration of a bit time for data transferred from said slave device to said master device, where said interface comprises a resistance R coupled between the serial data bidirectional signal line and a circuit ground, and a pull up resistance R_PU installed in the master device, wherein R and R_PU together form a resistor voltage divider network.

37. A master device comprising:

an interface for coupling to a slave device, the interface comprising a serial data bidirectional signal line;

wherein a reset signal is sent from the master device to the slave device over the serial data bidirectional signal line; and

a learning sequence signal is sent to the master device over the serial data bidirectional signal line for specifying a duration of a bit time for data transferred between the master device and the slave device;

wherein at least one of data and commands are communicated between the master device and the slave device over the serial data bidirectional signal line, and the interface comprises a resistance R coupled between the serial data bidirectional signal line and a circuit ground, and a pull up resistance R_PU installed in the master device, wherein R and R_PU together form a resistor voltage divider network, wherein presence of the resistance R affects the serial data bidirectional signal line to enable detection of a slave device connected/disconnected state.