Multi-processor type storage control apparatus for performing access control through selector

• US 7,167,949 B2
• Filed: 08/29/2005
• Issued: 01/23/2007
• Est. Priority Date: 04/27/1998
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Honma, Hisao, Fujimoto, Kazuhisa, Yamagami, Kenji, Kurosu, Yasuo
• Primary Examiner(s): Ellis; Kevin L.
• Application Number:
  US11/212,587
• Publication Number:
  US 20050283576A1
• Time in Patent Office: 512 Days
• Field of Search: 711/111, 711/112, 711/113, 711/114, 710/316, 710/317
• US Class Current: 711/111
• CPC Class Codes: G06F 11/1666 where the redundant component is memory or memory area
• CPC Class Codes: G06F 11/20 using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
• CPC Class Codes: G06F 11/201 between storage system components
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0626 Reducing size or complexity of storage systems
• CPC Class Codes: G06F 3/0658 Controller construction arrangements
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0683 Plurality of storage devices
• CPC Class Codes: G06F 3/0689 Disk arrays, e.g. RAID, JBOD

Abstract

A storage control apparatus is coupled to a central processing unit (CPU) and a storage unit to control input/output of data between the CPU and the storage unit. The storage control apparatus has at least two processors coupled to the CPU and the storage unit, a cashe memory (CM) unit for temporarily storing data of the storage unit, a shared memory (SM) unit for storing information concerning control of the CM unit and the storage unit, and a selector coupled to the at least two processors, the CM unit and the SM unit through access paths to selectively apply access requests from the at least two processors to the CM unit and the SM unit.

Claims

1. A storage system comprising:

a plurality of storage units; and

a control apparatus coupled to the plurality of storage units or a central processing unit,

wherein the control apparatus includes;

a plurality of processor sections coupled to the plurality of storage units or the central processing unit,

a plurality of selectors which are coupled to the plurality of processor sections and each of which has a plurality of buffers, and

a plurality of memories coupled to the plurality of selectors,

wherein each of the plurality of memories has a first region for storing data to be stored in the plurality of storage units and a second region for storing control information for controlling the storage system,

wherein each of the plurality of selectors, when receiving an access request for accessing to the second region from one of the plurality of processor sections, stores the data once into a corresponding one of the plurality of buffers thereof and sends the data thus stored to the one of the plurality of processor sections, and

wherein the plurality of buffers of each of the plurality of selectors are provided in one to one correspondence with the plurality of memories.

2. A storage system according to claim 1, wherein each of the plurality of selectors, when receiving data of an access request for accessing to the first region from one of the plurality of processor sections, sends the data to the one of the plurality of processor sections without using the buffer thereof.

3. A storage system according to claim 2,

wherein the first region and the second region of each of the plurality of memories are distinguished by addresses, and

wherein each of the plurality of selectors, in response to an address contained in the access request thus received, sends the access request thus received to the first region or the second region of one of the plurality of memories corresponding to the access request thus received.

4. A storage system according to claim 2,

wherein an access request received by each of the plurality of selectors includes information for designating the first region or the second region of each of the plurality of memories, and

wherein each of the plurality of selectors, in accordance with the information contained in the access request thus received, sends the access request thus received to the first region or the second region of one of the plurality of memories corresponding to the information.

5. A storage system according to claim 2,

wherein access requests received by each of the plurality of selectors include an access request according to a first protocol for accessing the first region and an access request according to a second protocol for accessing the second region, and

wherein each of the plurality of selectors, in accordance with the protocol of the access request thus received, sends the access request thus received to the first region or the second region of one of the plurality of memories corresponding to the protocol of the access request thus received.

6. A storage system according to claim 5,

wherein the plurality of processor sections are coupled to all of the plurality of selectors,

wherein the plurality of memories are coupled to all of the plurality of selectors, and

wherein a plurality of paths are provided independently in order to couple the plurality of processor sections, the plurality of selectors and the plurality of memories.

7. A storage system according to claim 6, wherein each of the plurality of selectors uses different ones of the plurality of paths between a case where sending an access request to the first region of each of the plurality of memories and a case where sending an access request to the second region of each of the plurality of memories.

8. A storage system comprising:

a plurality of storage units; and

a control apparatus coupled to the plurality of storage units or a central processing unit,

wherein the control apparatus includes;

a plurality of processor sections coupled to the plurality of storage units or the central processing unit,

a first selector which is coupled to the plurality of processor sections;

a second selector which is coupled to the plurality of processor sections and has a plurality of buffers, and

a plurality of memories coupled to the plurality of selectors,

wherein each of the plurality of memories has a first region for storing data to be stored in the plurality of storage units and a second region for storing control information for controlling the storage system,

wherein each of the plurality of selectors, when receiving an access request for accessing to the second region from one of the plurality of processor sections, stores the data once into a corresponding one of the plurality of buffers thereof and sends the data thus stored to the one of the plurality of processor sections,

wherein each of the plurality of selectors, when receiving an access request for accessing to the first region from one of the plurality of processor sections, sends the data to the one of the plurality of processor sections without using the buffer thereof, and

wherein the plurality of buffers of each of the plurality of selectors are provided in one to one correspondence with the plurality of memories.