Aggregate bandwidth through management using insertion of reset instructions for cache-to-cache data transfer
First Claim
1. A method for cache management in a shared memory multiprocessor environment to inhibit the occurrence of store misses during transfer of a store stream from a first cache to a second cache, the store stream including a plurality of cache lines having updated store elements, the method comprising the steps of:
- identifying a store stream for potential miss conditioning in a loop of an application code;
performing a cost analysis for calculating a threshold value for further consideration of the identified store stream for miss conditioning;
selecting the identified store stream for miss conditioning based on an accepted value for the threshold value; and
conditioning the selected store stream for miss inhibition by inserting a reset instruction in a corresponding loop of the selected store stream, the reset instruction for clearing at least one cache line in the second cache in advance of a store operation of the selected store stream;
wherein the reset instruction causes the environment to override an imposed store condition of a prefetch operation such that a previous version of the updated store elements is resident in the second cache in order to complete the store operation.
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Accused Products
Abstract
A method and system for reducing or avoiding store misses with a data cache block zero (DCBZ) instruction in cooperation with the underlying hardware load stream prefetching support for helping to increase effective aggregate bandwith. The method identifies and classifies unique streams in a loop based on dependency and reuse analysis, and performs loop transformations, such as node splitting, loop distribution or stream unrolling to get the proper number of streams. Static prediction and run-time profile information are used to guide loop and stream selection. Compile-time loop cost analysis and run-time check code and versioning are used to determine the number of cache lines ahead of each reference for data cache line zeroing and to tolerate required data alignment relative to data cache lines.
49 Citations
25 Claims
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1. A method for cache management in a shared memory multiprocessor environment to inhibit the occurrence of store misses during transfer of a store stream from a first cache to a second cache, the store stream including a plurality of cache lines having updated store elements, the method comprising the steps of:
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identifying a store stream for potential miss conditioning in a loop of an application code; performing a cost analysis for calculating a threshold value for further consideration of the identified store stream for miss conditioning; selecting the identified store stream for miss conditioning based on an accepted value for the threshold value; and conditioning the selected store stream for miss inhibition by inserting a reset instruction in a corresponding loop of the selected store stream, the reset instruction for clearing at least one cache line in the second cache in advance of a store operation of the selected store stream; wherein the reset instruction causes the environment to override an imposed store condition of a prefetch operation such that a previous version of the updated store elements is resident in the second cache in order to complete the store operation. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A system for cache management in a shared memory multiprocessor environment to inhibit the occurrence of store misses during transfer of a store stream from a first cache to a second cache, the store stream including a plurality of cache lines having updated store elements, the system comprising:
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an identification module for identifying the store stream for potential miss conditioning in a loop of an application code; a threshold module for performing a cost analysis for calculating a threshold value for further consideration of the identified store stream for miss conditioning; a selection module for selecting the store stream for miss conditioning based on an accepted value for the threshold value; and an insertion module for conditioning the selected store stream for miss inhibition by inserting a reset instruction in a corresponding loop of the selected store stream, the reset instruction for clearing at least one cache line in the second cache in advance of a store operation of the selected store stream; wherein the reset instruction causes the environment to override an imposed store condition of a prefetch operation such that a previous version of the updated store elements is resident in the second cache in order to complete the store operation. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24)
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25. A computer program product for cache management in a shared memory multiprocessor environment to inhibit the occurrence of store misses during transfer of a store stream from a first cache to a second cache, the store stream including a plurality of cache lines having updated store elements, the computer program product comprising:
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a computer readable medium; an identification module stored on the medium for identifying the store stream for potential miss conditioning in a loop of an application code; a threshold module stored on the medium for performing a cost analysis for calculating a threshold value for further consideration of the identified store stream for miss conditioning; a selection module coupled to the threshold module for selecting the store stream for miss conditioning based on an accepted value for the threshold value; and an insertion module coupled to the selection module for conditioning the selected store stream for miss inhibition by inserting a reset instruction in a corresponding loop of the selected store stream, the reset instruction for clearing at least one cache line in the second cache in advance of a store operation of the selected store stream; wherein the reset instruction causes the environment to override an imposed store condition of a prefetch operation such that a previous version of the updated store elements is resident in the second cache in order to complete the store operation.
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Specification