Method for forming a bond pad interface

• US 7,169,694 B2
• Filed: 08/03/2004
• Issued: 01/30/2007
• Est. Priority Date: 11/22/1999
• Status: Expired due to Term

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Kobayashi, Thomas S., Pozder, Scott K.
• Primary Examiner(s): Estrada; Michelle
• Application Number:
  US10/910,036
• Publication Number:
  US 20050014356A1
• Time in Patent Office: 910 Days
• Field of Search: 438/612, 257/E23.02
• US Class Current: 438/612
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05093 of a plurality of vias
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05171 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/05181 Tantalum [Ta] as principal constituent
• CPC Class Codes: H01L 2224/05184 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/05187 Ceramics, e.g. crystalline carbides, nitrides or oxides glass ceramics H01L2224/05188
• CPC Class Codes: H01L 2224/05558 conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05559 non conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05669 Platinum [Pt] as principal constituent
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01007 : Nitrogen [N]
• CPC Class Codes: H01L 2924/01012 : Magnesium [Mg]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01016 : Sulfur [S]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/0496 : 6th Group
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A composite bond pad that is resistant to external forces that may be applied during probing or packaging operations is presented. The composite bond pad includes a non-self-passivating conductive bond pad (134) that is formed over a semiconductor substrate (100). A dielectric layer (136) is then formed over the conductive bond pad (134). Portions of the dielectric layer (136) are removed such that the dielectric layer (136) becomes perforated and a portion of the conductive bond pad (134) is exposed. Remaining portions of the dielectric layer (136) form support structures (138) that overlie that bond pad. A self-passivating conductive capping layer (204) is then formed overlying the bond pad structure, where the perforations in the dielectric layer (136) allow for electrical contact between the capping layer (204) and the exposed portions of the underlying bond pad (134). The support structures (138) provide a mechanical barrier that protects the interface between the capping layer (204) and the bond pad (134). Additional mechanical robustness is achieved when the support structures (138) remain coupled to the unremoved portion of the dielectric layer (136), as forces buffered by the support structures (138) are distributed across the dielectric layer (136) and not concentrated at the bond pad location.

Claims

1. A method of forming a semiconductor device comprising:

forming a conductive bond pad over a semiconductor substrate, the conductive bond pad including a plurality of dielectric studs;

forming a dielectric layer over the conductive bond pad;

removing portions of the dielectric layer, wherein the removing portions of the dielectric layer forms a plurality of support structures that over lie the conductive bond pad, wherein the plurality of support structures are interconnected with unremoved portions of the dielectric layer;

forming a conductive capping layer overlying the plurality of support structures, wherein the conductive capping layer electrically contacts a portion of the conductive bond pad.

2. The method of claim 1 further comprising:

forming a barrier layer between the capping layer and the conductive bond pad.

3. The method of claim 2 wherein the barrier layer is formed after the removing portions of the dielectric layer but prior to the forming the conductive capping layer.

4. The method of claim 2 wherein the dielectric layer is characterized as a passivation layer.

5. A method of forming a semiconductor device, the method comprising:

forming a conductive bond pad over a semiconductor substrate, the conductive bond pad including a plurality of dielectric studs;

forming a dielectric layer over the conductive bond pad;

removing portions of the dielectric layer, wherein the removing portions of the dielectric layer forms a plurality of support structures that overlie the conductive bond pad;

forming a barrier layer overlying the conductive bond pad, the barrier layer electrically contacts the bond pad;

forming a conductive capping layer overlying the plurality of support structures and overlying the barrier layer;

wherein the removing portions of the dielectric layer defines a plurality of openings in the dielectric layer;

wherein a portion of the barrier layer is located in each opening of the plurality;

wherein a portion of the conductive capping layer is located in each opening of the plurality of openings.

6. The method of claim 5 further comprising:

wherein the forming the barrier layer is performed after the removing portions of the dielectric layer and prior to forming the conductive capping layer.

7. The method of claim 5 wherein the barrier layer electrically contacts the band pad.

8. The method of claim 5 wherein the removing portions of the dielectric layer includes exposing portions of the conductive bond pad, wherein the barrier layer abuts exposed portions of the conductive bond pad.

9. The method of claim 5 wherein the barrier layer includes at least one of a group of tantalum, titanium, tungsten, and chromium.

10. The method of claim 5 wherein the barrier layer includes tantalum.

11. The method of claim 5 wherein the conductive bond pad includes copper and the conductive capping layer includes aluminum.

12. The method of claim 5 wherein the plurality of support structures are interconnected with unremoved portions of the dielectric layer.

13. The method of claim 5 wherein the dielectric layer is characterized as a passivation layer.

14. A method of forming a semiconductor device, comprising:

forming a conductive bond pad over a semiconductor substrate, the conductive bond pad including a plurality of dielectric studs;

forming a dielectric layer over the conductive bond pad;

removing portions of the dielectric layer, wherein the removing portions of the dielectric layer forms a plurality of support structures that over lie the conductive bond pad, wherein each stud of the plurality is positioned beneath a support structure of the plurality;

forming a conductive capping layer overlying the plurality of support structures;

wherein for each support structure of the plurality, there is no conductive material between a support structure of the plurality and dielectric studs of the plurality positioned beneath the support structure.

15. The method of claim 14 wherein the plurality of support structures are interconnected with unremoved portions of the dielectric layer.

16. The method of claim 14 wherein the plurality of dielectric studs are positioned in the conductive bond pad in an arrayed format.

17. The method of claim 14 wherein the dielectric layer is characterized as a passivation layer.

18. A method of forming a semiconductor device, comprising:

forming a conductive bond pad over a semiconductor substrate, the conductive bond pad including a plurality of dielectric studs;

forming a dielectric layer over the conductive bond pad;

removing portions of the dielectric layer, wherein the removing portions of the dielectric layer forms a plurality of support structures that over lie the conductive bond pad, wherein each stud of the plurality is positioned beneath a support structure of the plurality;

forming a conductive capping layer overlying the plurality of support structures;

forming a barrier layer after the removing portions of the dielectric layer, wherein the capping layer overlies the barrier layer.

19. The method of claim 18 wherein:

the removing portions of the dielectric layer defines a plurality of openings in the dielectric layer;

a portion of the barrier layer is located in each opening of the plurality;

a portion of the conductive capping layer is located in each opening of the plurality.

20. The method of claim 18 wherein the removing portions of the dielectric layer includes exposing portions of the conductive bond pad, wherein the barrier layer contacts exposed portions of the conductive bond pad.

21. The method of claim 18 wherein the barrier layer extends between support structures of the plurality.

22. The method of claim 18 wherein for each support structure of the plurality, there is no conductive material between a support structure of the plurality and dielectric studs of the plurality positioned beneath the support structure.

23. The method of claim 18 wherein each stud of the plurality is positioned beneath a support structure of the plurality.

24. A method of forming a semiconductor device comprising:

forming a conductive bond pad over a substrate, the conductive bond pad including a plurality of dielectric studs;

forming a dielectric layer over the conductive bond pad;

removing portions of the dielectric layer to define a plurality of openings in the dielectric layer over the conductive bond pad;

forming a baffler layer over the dielectric layer, wherein a portion of the barrier layer is located in each of the plurality of openings;

forming a conductive capping layer over the barrier layer, wherein a portion of the conductive capping layer is located in each of the plurality of openings.

25. The method of claim 24 wherein none of the plurality of openings is located over a dielectric stud of the plurality.

26. The method of claim 24 wherein the dielectric layer is characterized as a passivation layer.

27. The method of claim 24 wherein for each dielectric stud of the plurality, there is no conductive material between the dielectric layer and the dielectric stud.

28. The method of claim 24 wherein the removing portions of the dielectric layer includes exposing portions of the conductive bond pad, wherein the barrier layer contacts exposed portions of the conductive bond pad.

29. A method of forming a semiconductor device comprising:

forming a conductive bond pad over a substrate, the conductive bond pad including a plurality of dielectric studs;

forming a dielectric layer over the conductive bond pad;

removing portions of the dielectric layer to define a plurality of openings in the dielectric layer over the conductive bond pad, wherein none of the plurality of openings is located over a dielectric stud of the plurality;

forming a conductive capping layer over the dielectric layer after the removing portions of the dielectric layer.

30. The method of claim 29 further comprising:

forming a barrier layer over the dielectric layer, wherein a portion of the barrier layer is located in each of the plurality of openings, wherein the barrier layer is formed prior to the forming the conductive capping layer.

31. The method of claim 29 wherein the dielectric layer is characterized as a passivation layer.

32. The method of claim 29 wherein for each dielectric stud of the plurality, there is no conductive material between the dielectric layer and the dielectric stud.

33. The method of claim 29 wherein the removing portions of the dielectric layer includes exposing portions of the conductive bond pad, wherein the barrier layer contacts exposed portions of the conductive bond pad.