Semiconductor constructions
First Claim
1. A semiconductor structure comprising:
- a dielectric layer on a substrate;
a gate structure over the dielectric layer, the gate structure comprising;
a polysilicon material layer;
a conductive reaction barrier layer over the polysilicon material layer; and
a metal layer over the conductive reaction barrier layer, the gate structure having a pair of sidewalls each comprising a polysilicon material surface and a metal-comprising surface;
a non-oxide spacer directly against each of the sidewalls, the non-oxide spacer comprising a first non-oxide material and a second non-oxide material and covering an entirety of the polysilicon material surface and the metal-comprising surface; and
an oxidized region of the polysilicon material adjacent the dielectric layer and each of the non-oxide spacers.
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Accused Products
Abstract
A semiconductor processing method of forming a conductive gate or gate line over a substrate includes, a) forming a conductive gate over a gate dielectric layer on a substrate, the gate having sidewalls and an interface with the gate dielectric layer; b) electrically insulating the gate sidewalls; and c) after electrically insulating the gate sidewalls, exposing the substrate to oxidizing conditions effective to oxidize at least a portion of the gate interface with the gate dielectric layer. According to one aspect of the invention, the step of exposing the substrate to oxidizing conditions is conducted after provision of a first insulating material and subsequent anisotropic etch thereof to insulate the gate sidewalls. According to another aspect of the invention, the step of exposing the substrate to oxidizing conditions is conducted after provision of first and second insulating materials and subsequent anisotropic etch thereof to insulate the gate sidewalls. According to another aspect of the invention, the step of exposing the substrate to oxidizing conditions is conducted after provision and subsequent anisotropic etch of a first insulating material, followed by provision and subsequent anisotropic etch of a second insulating material.
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Citations
12 Claims
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1. A semiconductor structure comprising:
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a dielectric layer on a substrate; a gate structure over the dielectric layer, the gate structure comprising; a polysilicon material layer; a conductive reaction barrier layer over the polysilicon material layer; and a metal layer over the conductive reaction barrier layer, the gate structure having a pair of sidewalls each comprising a polysilicon material surface and a metal-comprising surface; a non-oxide spacer directly against each of the sidewalls, the non-oxide spacer comprising a first non-oxide material and a second non-oxide material and covering an entirety of the polysilicon material surface and the metal-comprising surface; and an oxidized region of the polysilicon material adjacent the dielectric layer and each of the non-oxide spacers. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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Specification
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- Resources
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Current AssigneeRound Rock Research LLC
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Original AssigneeMicron Technology, Inc.
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InventorsPan, Pai-Hung
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Primary Examiner(s)Trinh; Michael
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Application NumberUS11/025,142Publication NumberTime in Patent Office763 DaysField of Search438/595, 257/413, 257/412, 257/388, 257/383US Class Current257/412CPC Class CodesH01L 21/28167 on single crystalline silic...H01L 21/28176 with a treatment, e.g. anne...H01L 21/28211 in a gaseous ambient using ...
