Hysteresis comparator circuit

• US 7,170,330 B2
• Filed: 01/27/2005
• Issued: 01/30/2007
• Est. Priority Date: 01/27/2004
• Status: Active Grant

• Current Assignee: DENSO Corporation
• Original Assignee: DENSO Corporation
• Inventors: Kamei, Syunji
• Primary Examiner(s): Lam; Tuan T.
• Assistant Examiner(s): Nguyen; Hiep
• Application Number:
  US11/043,233
• Publication Number:
  US 20050162207A1
• Time in Patent Office: 733 Days
• Field of Search: None
• US Class Current: 327/205
• CPC Class Codes: H03K 3/02337 Bistables with hysteresis, e.g. Schmitt trigger non-regenerative amplitude discriminators G01R19/165
• CPC Class Codes: H03K 5/088 modified by switching, e.g. by a periodic signal or by a signal in synchronism with the transitions of the output signal

Abstract

An input voltage is applied to an inverting input terminal of a comparator having no hysteresis. A first constant voltage is divided by resistors to create a reference voltage. The reference voltage is applied to a non-inverting input terminal of the comparator through a resistor. Only while an output voltage of the comparator is a low level, a predetermined constant current is supplied to a supply point of the reference voltage and a constant current of the same magnitude is absorbed from the non-inverting input terminal of the comparator.

Claims

1. A hysteresis comparator circuit comprising:

a comparator that outputs a H-level voltage when a voltage applied to its non-inverting input terminal is equal to or larger than a voltage applied to its inverting input terminal, and outputs a L-level voltage when the above condition is not satisfied;

first and second resistors connected in series between a potential reference line and a first power line for supplying a first constant voltage being set based on an electric potential of the potential reference line in this order, with the first resistor connected to the first power line;

a third resistor connected between an interconnection point of the first and second resistors and the non-inverting input terminal of the comparator;

a first constant current source circuit for supplying a predetermined constant current to the interconnection point only while the output voltage of the comparator is the L-level; and

a second constant current source circuit for absorbing a constant current equal to the constant current supplied by the first constant current source circuit from the non-inverting input terminal of the comparator only while the output voltage of the comparator is the L-level,

wherein an input voltage that is set based on the electric potential of the potential reference line is applied to the inverting input terminal of the comparator.

3. The hysteresis comparator circuit according to claim 1, wherein:

the first constant current source circuit is constructed with a diode whose cathode is connected to the interconnection point of the first and second resistors, a first constant current source for always supplying a predetermined constant current to an anode of the diode, and a first NPN transistor that is connected between the anode of the diode and the potential reference line and is configured to be conductive only while the output voltage of the comparator is the H level; and

the second constant current source circuit is constructed with a second NPN transistor connected between the non-inverting input terminal of the comparator and the potential reference line, a third NPN transistor whose base and corrector are connected to a base of the second NPN transistor and whose emitter is connected to the potential reference line, a second constant current source for always supplying a constant current of the same magnitude as that of the constant current outputted by the first constant current source to a collector of the third NPN transistor, and a fourth NPN transistor that is connected between the collector of the third NPN transistor and the potential reference line and configured to become conductive only while the output voltage of the comparator is the H level.

5. The hysteresis comparator circuit according to claim 3, wherein:

each of the first and second constant current sources is constructed as a constant current source circuit of a current mirror configuration that uses first and second PNP transistors having identical electric characteristics, a third PNP transistor, and a fourth resistor;

emitters of the first, second and third PNP transistors are all connected to a second power line that supplies a second constant voltage being set based on the electric potential of the potential reference line, bases thereof are connected together and connected to a collector of the third PNP transistor;

a collector of the first PNP transistor is connected to the anode of the diode, a collector of the second PNP transistor is connected to the collector of the third NPN transistor; and

the fourth resistor is connected between the collector of the third PNP transistor and the potential reference line.

7. The hysteresis comparator circuit according to claim 3, wherein:

each of the first and second constant current sources is constructed as a constant current source circuit of a current mirror configuration that uses first and second PNP transistors having identical electric characteristics, a third PNP transistor, and a fourth resistor;

emitters of the first, second and third PNP transistors are all connected to a second power line that supplies a second constant voltage being set based on the electric potential of the potential reference line, bases thereof are connected together and connected to a collector of the third PNP transistor;

a collector of the first PNP transistor is connected to the anode of the diode, a collector of the second PNP transistor is connected to the collector of the third NPN transistor;

a fifth NPN transistor and a fifth resistor are connected in series between the collector of the third PNP transistor and the potential reference line, with the fifth resistor connected to the potential reference line; and

a sixth resistor is connected between a base of the fifth NPN transistor and the second power line, a fourth PNP transistor is connected between the base thereof and the potential reference line, and a third constant voltage is applied to a base of the fourth PNP transistor.

2. A hysteresis comparator circuit comprising:

a comparator that outputs a H-level voltage when a voltage applied to its non-inverting input terminal is equal to or larger than a voltage applied to its inverting input terminal, and outputs a L-level voltage when the above condition is not satisfied;

first and second resistors connected in series between a potential reference line and a first power line for supplying a first constant voltage being set based on an electric potential of the potential reference line in this order, with the first resistor connected to the first power line;

a third resistor connected between an interconnection point of the first and second resistors and the inverting input terminal of the comparator;

a first constant current source circuit for supplying a predetermined constant current to the inverting input terminal only while the output voltage of the comparator is the L-level; and

a second constant current source circuit for absorbing a constant current equal to the constant current supplied by the first constant current source circuit from the connection point between the first resistor and the second resistor only while the output voltage of the comparator is the L-level,

wherein an input voltage that is set based on the electric potential of the potential reference line is applied to the non-inverting input terminal of the comparator.

4. The hysteresis comparator circuit according to claim 2, wherein:

the first constant current source circuit is constructed with a diode whose cathode is connected to the inverting input terminal of the comparator, a first constant current source for always supplying a predetermined constant current to an anode of the diode, and a first NPN transistor that is connected between the anode of the diode and the potential reference line and is configured to be conductive only while the output voltage of the comparator is the H level; and

the second constant current source circuit is constructed with a second NPN transistor connected between the connection point of the first resistor and the second resistor and the potential reference line, a third NPN transistor whose base and corrector are connected to a base of the second NPN transistor and whose emitter is connected to the potential reference line, a second constant current source for always supplying a constant current of the same magnitude as that of the constant current outputted by the first constant current source to a collector of the third NPN transistor, and a fourth NPN transistor that is connected between the collector of the third NPN transistor and the potential reference line and configured to become conductive only while the output voltage of the comparator is the H level.

6. The hysteresis comparator circuit according to claim 4, wherein:

each of the first and second constant current sources is constructed as a constant current source circuit of a current mirror configuration that uses first and second PNP transistors having identical electric characteristics, a third PNP transistor, and a fourth resistor;

emitters of the first, second and third PNP transistors are all connected to a second power line that supplies a second constant voltage being set based on the electric potential of the potential reference line, bases thereof are connected together and connected to a collector of the third PNP transistor;

a collector of the first PNP transistor is connected to the anode of the diode, a collector of the second PNP transistor is connected to the collector of the third NPN transistor; and

the fourth resistor is connected between the collector of the third PNP transistor and the potential reference line.

8. The hysteresis comparator circuit according to claim 4, wherein:

each of the first and second constant current sources is constructed as a constant current source circuit of a current mirror configuration that uses first and second PNP transistors having identical electric characteristics, a third PNP transistor, and a fourth resistor;

emitters of the first, second and third PNP transistors are all connected to a second power line that supplies a second constant voltage being set based on the electric potential of the potential reference line, bases thereof are connected together and connected to a collector of the third PNP transistor;

a collector of the first PNP transistor is connected to the anode of the diode, a collector of the second PNP transistor is connected to the collector of the third NPN transistor;

a collector of the first PNP transistor is connected to the anode of the diode, a collector of the second PNP transistor is connected to the collector of the third NPN transistor;

a fifth NPN transistor and a fifth resistor are connected in series between the collector of the third PNP transistor and the potential reference line, with the fifth resistor connected to the potential reference line; and

a sixth resistor is connected between a base of the fifth NPN transistor and the second power line, a fourth PNP transistor is connected between the base thereof and the potential reference line, and a third constant voltage is applied to a base of the fourth PNP transistor.

9. A hysteresis comparator circuit comprising:

a comparator that outputs a H-level voltage when a voltage applied to its non-inverting input terminal is equal to or more than a voltage applied to its inverting input terminal, and outputs a L-level voltage when the above condition is not satisfied;

first and second resistors connected in series between a potential reference line and a first power line for supplying a first constant voltage being set based on an electric potential of the potential reference line, with the first resistor connected to the first power line;

a third resistor connected between an interconnection point of the first and second resistors and the non-inverting input terminal of the comparator;

a first constant current source circuit for supplying a predetermined constant current to the non-inverting input terminal only while the output voltage of the comparator is the H-level; and

a second constant current source circuit for absorbing a constant current equal to the constant current supplied by the first constant current source circuit from the interconnection point only while the output voltage of the comparator is the H-level,

wherein an input voltage that is set based on the electric potential of the potential reference line is applied to the inverting input terminal of the comparator.

11. The hysteresis comparator circuit according to claim 9, wherein:

the first constant current source circuit is a constant current source circuit of a current mirror structure that includes first and second PNP transistors whose emitters are both connected to the second power line and whose bases are connected together;

the first constant current source circuit being configured so that a current proportional to the collector current of the first PNP transistor is made to output from a collector of the second PNP transistor; and

wherein the second constant current source circuit is a constant current source circuit constructed with a current mirror circuit including a third PNP transistor having identical electric characteristics to those of the second PNP transistor and the first PNP transistor whose emitters are connected together and whose bases are connected together, the current mirror circuit being configured so that a current proportional to a collector current of the first PNP transistor is made to output from a collector of the third PNP transistor; and

a current mirror circuit including the fourth and fifth NPN transistors having identical electric characteristics, whose emitters are both connected to the potential reference line and whose bases are both connected to a collector of the fifth NPN transistor, a collector of the fourth NPN transistor being connected to the interconnection point of the first and second resistors, and the collector of the fifth NPN transistor being connected to the collector of the third PNP transistor, the current mirror circuit being configured so that a current equal to a current flowing into the collector of the fifth NPN transistor is made to flow in the fourth NPN transistor;

the second constant current source circuit being configured so as to absorb a current proportional to the collector current of the first PNP transistor from the fourth NPN transistor; and

the fourth resistor and the sixth NPN transistor are connected in series between the collector of the first PNP transistor and the potential reference line, with the fourth resistor connected to the collector, and the sixth NPN transistor becomes conductive only while the output voltage of the comparator is the H level.

10. A hysteresis comparator circuit comprising:

a comparator that outputs a H-level voltage when a voltage applied to its non-inverting input terminal is equal to or more than a voltage applied to its inverting input terminal, and outputs a L-level voltage when the above condition is not satisfied;

first and second resistors connected in series between a potential reference line and a first power line for supplying a first constant voltage being set based on an electric potential of the potential reference line, with the first resistor connected to the first power line;

a third resistor connected between an interconnection point of the first and second resistors and the inverting input terminal of the comparator;

a first constant current source circuit for supplying a predetermined constant current to the connection point of the first resistor and the second resistor only while the output voltage of the comparator is the H-level; and

a second constant current source circuit for absorbing a constant current equal to the constant current supplied by the first constant current source circuit from the inverting input terminal only while the output voltage of the comparator is the H-level,

wherein an input voltage that is set based on the electric potential of the potential reference line is applied to the non-inverting input terminal of the comparator.

12. The hysteresis comparator circuit according to claim 10, wherein:

the first constant current source circuit is a constant current source circuit of a current mirror structure that includes first and second PNP transistors whose emitters are both connected to the second power line and whose bases are connected together;

the first constant current source circuit being configured so that a current proportional to the collector current of the first PNP transistor is made to output from a collector of the second PNP transistor; and

wherein the second constant current source circuit is a constant current source circuit constructed with a current mirror circuit including a third PNP transistor having identical electric characteristics to those of the second PNP transistor and the first PNP transistor whose emitters are connected together and whose bases are connected together, the current mirror circuit being configured so that a current proportional to a collector current of the first PNP transistor is made to output from a collector of the third PNP transistor; and

a current mirror circuit including the fourth and fifth NPN transistors having identical electric characteristics, whose emitters are both connected to the potential reference line and whose bases are both connected to a collector of the fifth NPN transistor, a collector of the fourth NPN transistor being connected to the interconnection point of the first and second resistors, and the collector of the fifth NPN transistor being connected to the collector of the third PNP transistor, the current mirror circuit being configured so that a current equal to a current flowing into the collector of the fifth NPN transistor is made to flow in the fourth NPN transistor;

the second constant current source circuit being configured so as to absorb a current proportional to the collector current of the first PNP transistor from the fourth NPN transistor; and

the fourth resistor and the sixth NPN transistor are connected in series between the collector of the first PNP transistor and the potential reference line, with the fourth resistor connected to the collector, and the sixth NPN transistor becomes conductive only while the output voltage of the comparator is the H level.