Fast LUT predistorter for power amplifier

• US 7,170,343 B2
• Filed: 05/27/2004
• Issued: 01/30/2007
• Est. Priority Date: 12/27/2003
• Status: Expired due to Fees

• Current Assignee: Electronics and Telecommunications Research Institute
• Original Assignee: Electronics and Telecommunications Research Institute
• Inventors: Kim, Soo-Young, Ahn, Do-Seob, Lee, Seong-Pal, Oh, Deock-Gil, Jin, Ming-Lu, Kim, Jae-Moung
• Primary Examiner(s): Pascal; Robert
• Assistant Examiner(s): NGUYEN, HIEU P
• Application Number:
  US10/856,240
• Publication Number:
  US 20050140438A1
• Time in Patent Office: 978 Days
• Field of Search: 330/149, 330/296, 455/114.3
• US Class Current: 330/149
• CPC Class Codes: H03F 1/3241 using predistortion circuits H03F1/3211, H03F1/3217 take precedence

Abstract

A fast LUT predistortion apparatus and method for compensating nonlinear distortion of the high power amplifier HPA is disclosed. The apparatus includes a predistortion unit for predistorting an input complex digital signal based on a look up table LUT implementation and outputting a predistorted complex signal; and a power amplifier for amplifying the predistorted signal and outputting an amplified complex signal.

Claims

1. A fast look up table (LUT) predistortion apparatus comprising:

a predistortion means for predistorting an input complex digital signal based on an LUT implementation and outputting a predistorted complex signal; and

a power amplifier for amplifying the predistorted signal and outputting an amplified complex signal,

wherein the predistortion means includes;

a selection unit for receiving the input complex digital signal, generating an access point and a quantized signal based on the input complex digital signal;

a memory unit for storing values of the input complex digital signal corresponding to the accessing point from the selection unit and outputting a stored signal;

a multiplexer for generating a multiplexed signal by selecting one of the stored signal and the input digital complex signal;

a address generator for generating an access point according to the quantized signal from the selection unit;

a LUT for storing complex gain values according to the access point from the address generator and outputting stored complex gain value;

a multiplier for multiplying the multiplexed signal from the multiplexer and stored complex gain value from the LUT;

a delayer for receiving the multiplexed signal, and generating a delayed signal by delaying the multiplexed signal to match a feedback signal from the power amplifier;

a adaptation unit for calculating an error signal by comparing the delayed signal and the feedback signal and updating the complex gain values of the LUT; and

a control unit for controlling the selection unit and multiplexer by state of the error signal from the adaptation unit.

2. The fast look up table predistortion apparatus of claim 1, wherein contents of the memory unit are subdivision points of the inverse characteristics of the power amplifier and is predefined in terms of characteristics of real power amplifier.

3. The fast look up table predistortion apparatus of claim 1, wherein the contents of look up table (LUT) a recalculated in terms of the inverse characteristics of the power amplifier that inducted from real measurement of characteristics of a real power amplifier or initialized by linear interpolation by minimum and maximum input-output value.

4. The fast look up table predistortion apparatus of claim 1, wherein the error signal e_F(F)in the adaptation unit is calculated by a function as:

$e_f<br><br>\left(F\right)=\frac{v_a}{v_i-K}$

where v_i shows the input complex signal to multiplier, v_a represents the feedback signal from output of power amplifier and K depicts the gain of power amplifier.

5. A fast look up table (LUT) predistortion method comprising:

an acquisition step for selecting LUT access points and performing a predistortion and updating operation with the selected access points; and

a tracking step for performing the predistortion and updating operation with an input complex digital signal

wherein the acquisition step includes

a reset step for performing the predistortion and updating operation without the input complex digital signal and generating accessing points to a memory unit in a predefined order; and

an error severe step for performing the predistortion and updating operation with the input complex signal and generating accessing points to the memory unit based on values of the input complex digital signal.

6. The fast look up table predistortion method of claim 5, wherein the reset step is performed, if a system using the fast LUT predistortion method is powered on or reset.

7. The fast look up table predistortion method of claim 5, wherein the error severe step is performed, if an error calculated by an adaptation algorithm is greater than a predefined threshold.

8. The fast look up table predistortion method of claim 7, wherein the error calculated is an average error of several samples.