Image processing apparatus, image processing method and portable imaging apparatus

• US 7,170,553 B2
• Filed: 04/26/2002
• Issued: 01/30/2007
• Est. Priority Date: 04/26/2001
• Status: Expired due to Fees

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Takai, Kensuke, Matsuki, Hiroyuki
• Primary Examiner(s): MOE, AUNG SOE
• Application Number:
  US10/132,267
• Publication Number:
  US 20020159656A1
• Time in Patent Office: 1,740 Days
• Field of Search: 348/222.1, 348/231.99, 348/231.9, 348/294, 382/305, 382/299, 382/232, 382/293, 382/297, 710/22, 712/25, 712/1
• US Class Current: 348/222.1
• CPC Class Codes: G06T 1/60 Memory management

Abstract

An apparatus for processing an image includes a memory for storing the image data of each pixel in the plurality of unit blocks, a direct memory access controller for reading the image data from the memory by accessing the memory on a block-by-block basis by generating the addresses of the pixels in each unit block, and a plurality of image processing modules for receiving the image data of each unit block read based on the addresses generated by the direct memory access controller and sequentially transferred via a data bus, processing the image data of the unit block, and outputting the processed image data of the unit block.

Claims

1. An apparatus for processing an image, wherein the image includes a plurality of unit blocks each containing M×

N pixels where M pixels are arranged in a horizontal direction and N pixels are arranged in a vertical direction, the apparatus comprising;

a memory for storing the image data of each pixel in the plurality of unit blocks;

a direct memory access controller for reading the image data from the memory by accessing the memory on a block-by-block basis by generating the addresses of the pixels in each unit block; and

a plurality of image processing modules for receiving the image data of each unit block read based on the addresses generated by the direct memory access controller and sequentially transferred via a data bus, processing the image data of the unit block, and outputting the processed image data of the unit block,

wherein the direct memory access controller sequentially generates the addresses of the pixels in one horizontal line in each unit block and thereafter generates the addresses of the pixels on another horizontal line immediately below said one horizontal line in the unit block, and repeats this operation to read the image data of the unit block, and

the direct memory access controller sequentially reads the image data of the unit blocks in one horizontal line in the image and thereafter sequentially reads the image data of the unit blocks on another horizontal line immediately below said one horizontal line in the image, and repeats this operation to read the data of the image.

2. An apparatus according to claim 1, wherein the direct memory access controller comprises:

a plurality of registers for storing the number of pixels in one horizontal line in one unit block, the number of pixels in one vertical line in one unit block, the number of blocks in one horizontal line in the image, an address increment representing an address space of the memory between the address of one pixel and the address of another pixel immediately below said one pixel, a data transfer initiation address, and a data transfer completion address, respectively;

a plurality of counters for determining the horizontal and vertical coordinates of the pixels in each unit block, the ordinal number in the horizontal direction of the unit block, and the ordinal number in the vertical direction of the unit block, respectively, wherein the pixels correspond to the input/output data of the memory; and

an address calculating section for calculating each address based on the values stored in the plurality of registers and values counted by the plurality of counters.

3. An apparatus according to claim 2, wherein the number of pixels in one horizontal line in one unit block being input to or output from the image processing module and the number of pixels in one vertical line in said unit, both numbers being obtained from the plurality of image processing modules, are stored in the respective registers of the direct memory access controller.

4. An apparatus according to claim 1, wherein the image processing module comprises at least:

an input buffer;

an output buffer;

a direct memory access request outputting section for outputting a direct memory access request for data input to the direct memory access controller when the data of one unit block stored in the input buffer remains small, and outputting a direct memory access request for data output to the direct memory access controller when a predetermined amount of the data of one unit block is stored in the output buffer.

5. An apparatus according to claim 1, wherein the direct memory access controller further comprises a register for storing the number of pixels on a vertical line from the uppermost line of one unit block to the uppermost line of another block immediately below said one block, wherein from the uppermost line of said another block, data transfer is initiated again after the image data of all of the unit blocks in one horizontal line in the image has been transferred.

6. A portable imaging apparatus comprising an image capturing section including a charge coupled device and an image processing apparatus according to claim 1, wherein the image processing apparatus processes the data of an image captured by the charge coupled device.

7. A method for processing an image using an apparatus for processing an image, wherein the image includes a plurality of unit blocks each containing M×

N pixels where M pixels are arranged in a horizontal direction and N pixels are arranged in a vertical direction, the method comprising;

storing in a memory the image data of each pixel in the plurality of unit blocks;

reading the image data from the memory by accessing the memory on a block-by-block basis by generating the addresses of the pixels in each unit block by a direct memory access controller; and

receiving the image data of each unit block read based on the addresses generated by the direct memory access controller and sequentially transferred via a data bus, processing the image data of the unit block, and outputting the processed image data of the unit block,

wherein the direct memory access controller sequentially generates the addresses of the pixels in one horizontal line in each unit block and thereafter generates the addresses of the pixels on another horizontal line immediately below said one horizontal line in the unit block, and repeats this operation to read the image data of the unit block, and

the direct memory access controller sequentially reads the image data of the unit blocks in one horizontal line in the image and thereafter sequentially reads the image data of the unit blocks on another horizontal line immediately below said one horizontal line in the image, and repeats this operation to read the data of the image.