Direct conversion receiver and DC offset reducing method

• US 7,171,185 B2
• Filed: 01/28/2003
• Issued: 01/30/2007
• Est. Priority Date: 01/29/2002
• Status: Expired due to Fees

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Matsumoto, Hidenori, Obara, Toshio
• Primary Examiner(s): Urban; Edward F.
• Assistant Examiner(s): Le; Nhan T.
• Application Number:
  US10/469,290
• Publication Number:
  US 20040097212A1
• Time in Patent Office: 1,463 Days
• Field of Search: 455/232.1, 455/234.1, 455/240.1, 455/243.1, 455/245.1, 455/250.1, 455/266, 455/296, 455/311, 455/312, 455/313, 455/323, 455/324, 455/334, 455/338, 455/341, 455/339, 455/340, 375/345
• US Class Current: 455/324
• CPC Class Codes: H03G 3/3068 Circuits generating control signals for both R.F. and I.F. stages
• CPC Class Codes: H04B 1/30 for homodyne or synchrodyne receivers demodulator circuits H03D1/22
• CPC Class Codes: H04B 2201/70707 Efficiency-related aspects
• CPC Class Codes: H04L 25/06 Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
• CPC Class Codes: H04L 27/3809 Amplitude regulation arrangements

Abstract

A determining section (18) and gain variation amount detecting section (9) detect a period having a possibility of a DC-component offset in an internal circuit of a direct conversion receiver increasing beyond an allowable value due to AGC operation, and during the period, a cut-off frequency of each of high-pass filters (12a to 12d) is set at a frequency higher than that in general operation, thereby rapidly converging transient responses of signals passed through the high-pass filters, while controlling precisely operation timings of reception power measuring section (16), gain calculating section (22), gain control section (23) and circuit power supply control section (24) composing an AGC loop, whereby the DC offset is prevented from increasing and stable circuit operation is assured. It is thereby possible to achieve further reductions in size and power consumption of a CDMA receiver using the direct conversion receiver.

Claims

1. An AGC circuit in a direct conversion receiver for multiplying a received high-frequency signal by a local signal with a frequency substantially the same as that of the high-frequency signal to directly convert into a baseband signal, amplifying the baseband signal using a baseband variable gain amplifying circuit having a variable gain amplifier, low-pass filter and a high-pass filter for cutting off a DC component as structural elements, and performing A/D conversion and demodulation on the resultant, the AGC circuit comprising:

a power measuring section that measures reception power based on a signal subjected to A/D conversion;

a gain calculating section that calculates a gain of the variable gain amplifier using information of a difference between measured reception power and a target convergence value;

a gain control section that controls the gain of the variable gain amplifier based on the calculated gain;

a filter control section that has a function of switching a cut-off frequency of the high-pass filter between at least high-and-low two frequencies; and

a gain variation amount detecting section that reports to the filter control section upon detecting that the gain of the variable gain amplifier varies by an amount equal to or greater than a predetermined amount as a result of control by the gain control section, wherein;

the filter control section switches the cut-off frequency of the high-pass filter to a high frequency upon receiving the report from the gain variation amount detecting section; and

the gain calculating section and the gain control section perform at least one of processing for increasing a range of gain variation per update and processing for shortening a period of the update during a period of time the cut-off frequency of the high-pass filter is switched to the high frequency.

2. The AGC circuit in the direct conversion receiver according to claim 1, wherein:

the filter control section switches the cut-off frequency of the high-pass filter to the high frequency and then switches the cut-off frequency to a low frequency again; and

the power measuring section does not measure reception power during a period of time the cut-off frequency of the high-pass filter is switched to the high frequency in a predetermined period in measuring average reception power for the predetermined period.

3. A CDMA receiver provided with the AGC circuit in the direct conversion receiver according to claim 1.

4. An AGC circuit in a direct conversion receiver for multiplying a received high-frequency signal by a local signal with a frequency substantially the same as that of the high-frequency signal to directly convert into a baseband signal, amplifying the baseband signal using a baseband variable gain amplifying circuit having a variable gain amplifier, low-pass filter and a high-pass filter for cutting off a DC component as structural elements, and performing A/D conversion and demodulation on the resultant, the AGC circuit comprising:

a power measuring section that measures reception power based on a signal subjected to A/D conversion;

a gain calculating section that calculates a gain of the variable gain amplifier using information of a difference between measured reception power and a target convergence value;

a gain control section that controls the gain of the variable gain amplifier based on the calculated gain;

a filter control section that has a function of switching a cut-off frequency of the high-pass filter between at least high-and-low two frequencies; and

a determining section that determines whether or not there is a high possibility of increasing a DC offset of a signal passed through the high-pass filter, based on information contained in a demodulated signal, or based on an operation state of the direct conversion receiver, and reports the determination result to the filter control section, wherein;

the filter control section switches the cut-off frequency of the high-pass filter to the high frequency upon receiving the report from the determining section; and

the gain calculating section and the gain control section perform at least one of processing for increasing a range of gain variation per update and processing for shortening a period of the update during a period of time the cut-off frequency of the high-pass filter is switched to the high frequency.

5. The AGC circuit in the direct conversion receiver according to claim 4, wherein:

the filter control section switches the cut-off frequency of the high-pass filter to the high frequency and then switches the cut-off frequency to a low frequency again; and

the power measuring section does not measure reception power during a period of time the cut-off frequency of the high-pass filter is switched to the high frequency in a predetermined period in measuring average reception power for the predetermined period.

6. A CDMA receiver provided with the AGC circuit in the direct conversion receiver according to claim 4.

7. A baseband variable gain amplifying circuit that is provided in a direct conversion receiver and that amplifies a baseband signal, comprising:

a variable gain amplifier that amplifies the baseband signal;

a high-pass filter that cuts off a DC component existing on a signal path of the baseband signal and that enables a cut-off frequency to be varied between at least low-and-high two frequencies;

a gain variation amount detecting section that detects an amount of gain variation at which the variable gain amplifier is set equal to or greater than a predetermined amount;

a filter control section that switches the cut-off frequency of the high-pass filter to a high frequency when the gain variation amount detecting section detects that the amount of gain variation is equal to or greater than the predetermined amount; and

a gain control section that performs at least one of processing for increasing a range of gain variation per update and processing for shortening a period of the update during a period of time the cut-off frequency of the high-pass filter is switched to the high frequency.

8. A baseband variable gain amplifying circuit that is provided in a direct conversion receiver and that amplifies a baseband signal, comprising:

a variable gain amplifier that amplifies the baseband signal;

a high-pass filter that cuts off a DC component existing on a signal path of the baseband signal and that enables a cut-off frequency to be varied between at least low-and-high two frequencies;

a D/A converter that converts data of a gain at which the variable gain amplifier is set and digital data including data for instructing switching of the cut-off frequency of the high-pass filter into an analog signal;

a filter control section that switches the cut-off frequency of the high-pass filter based on a signal corresponding to the data for instructing switching of the cut-off frequency; and

a gain control section that performs at least one of processing for increasing a range of gain variation per update and processing for shortening a period of the update during a period of time the cut-off frequency of the high-pass filter is switched to the high frequency.