Method for managing resources in a reconfigurable computer having programmable logic resources where automatically swapping configuration data between a secondary storage device and the programmable logic resources

• US 7,171,548 B2
• Filed: 09/19/2003
• Issued: 01/30/2007
• Est. Priority Date: 11/20/1998
• Status: Expired

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Smith, Stephen J, Southgate, Timothy J
• Primary Examiner(s): Cao; Chun
• Assistant Examiner(s): SURYAWANSHI, SURESH
• Application Number:
  US10/666,948
• Publication Number:
  US 20040098569A1
• Time in Patent Office: 1,229 Days
• Field of Search: 713/1, 713/100, 712/15, 712/30, 712/37, 716/16, 716/17, 710/104, 710/8, 326/37, 326/38, 326/39
• US Class Current: 713/1
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

A reconfigurable computer system based on programmable logic is provided. A system design language may be used to write applications. The applications may be automatically partitioned into software components and programmable logic resource components. A virtual computer operating system may be provided to schedule and allocate system resources. The virtual computer operating system may include a virtual logic manager that may increase the capabilities of programmable logic resources in the system.

Claims

1. A method for managing resources in a reconfigurable computer that contains programmable logic resources that are reconfigurable to optimize the ability of the computer to handle a given application comprising:

automatically swapping configuration data between a secondary storage device and the programmable logic resources during programmable logic resource allocation using a virtual logic manager, wherein the secondary storage device is a mass storage device.

2. The method defined in claim 1 wherein the reconfigurable computer includes a central processing unit implemented on at least one programmable logic device and programmable logic coupled to the central processing unit, wherein the programmable logic is reconfigurable to optimize the ability of the computer system to handle a given application.

3. The method defined in claim 1 wherein the reconfigurable computer includes a central processing unit implemented on a microprocessor and programmable logic coupled to the central processing unit, wherein the programmable logic is reconfigurable to optimize the ability of the computer system to handle a given application.

4. The method defined in claim 1 wherein the reconfigurable computer includes a central processing unit that is partially implemented on a microprocessor and that is partially implemented on a programmable logic device and programmable logic coupled to the central processing unit, wherein the programmable logic is reconfigurable to optimize the ability of the computer system to handle a given application.

5. The method defined in claim 1 wherein the automatically swapping configuration data between the secondary storage device and the programmable logic resources comprises automatically swapping configuration data between a hard disk drive and the programmable logic resources.

6. The method defined in claim 1 wherein the automatically swapping configuration data between the secondary storage device and the programmable logic resources comprises automatically swapping configuration data between the secondary storage device and programmable logic device configuration memory.

7. The method defined in claim 1 further comprising automatically swapping state information between the secondary storage device and the programmable logic resources during programmable logic resource allocation using the virtual logic manager.

8. The method defined in claim 1 wherein the reconfigurable computer is scalable with respect to the programmable logic resources.