Comparison of circuit layout designs
First Claim
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1. A machine-accessible medium that provides instructions, which when executed by a computing platform, cause said computing platform to perform operations comprising a method of:
- obtaining a first circuit layout design;
obtaining a second circuit layout design;
generating a first topology graph for said first circuit layout design;
generating a second topology graph for said second circuit layout design;
comparing said first topology graph and said second topology graph to obtain a comparison result, wherein said comparison result comprises at least a first matched topology graph node pair and a second matched topology graph node pair connected via a topology graph line pair, said topology graph line pair having a pair of lengths and a pair of widths, wherein said method further comprises;
comparing said pair of lengths to a length sensitivity parameter; and
comparing said pair of widths to a width sensitivity parameter; and
reporting said comparison result.
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Abstract
A first circuit layout design is obtained, and a second circuit layout design is obtained. A first topology graph is generated for the first circuit layout design, and a second topology graph is generated for the second circuit layout design. The first topology graph and the second topology graph are compared to obtain a comparison result. The comparison result is reported.
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Citations
32 Claims
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1. A machine-accessible medium that provides instructions, which when executed by a computing platform, cause said computing platform to perform operations comprising a method of:
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obtaining a first circuit layout design; obtaining a second circuit layout design; generating a first topology graph for said first circuit layout design; generating a second topology graph for said second circuit layout design; comparing said first topology graph and said second topology graph to obtain a comparison result, wherein said comparison result comprises at least a first matched topology graph node pair and a second matched topology graph node pair connected via a topology graph line pair, said topology graph line pair having a pair of lengths and a pair of widths, wherein said method further comprises; comparing said pair of lengths to a length sensitivity parameter; and comparing said pair of widths to a width sensitivity parameter; and
reporting said comparison result. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method comprising:
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obtaining a first circuit layout design; obtaining a second circuit layout design; generating a first topology graph for said first circuit layout design; generating a second topology graph for said second circuit layout design; comparing said first topology graph and said second topology graph to obtain a comparison result, wherein said comparison result comprises at least a first matched topology graph node pair and a second matched topology graph node pair connected via a topology graph line pair, said topology graph line pair having a pair of lengths and a pair of widths, wherein said method further comprises; comparing said pair of lengths to a length sensitivity parameter; and comparing said pair of widths to a width sensitivity parameter; and
reporting said comparison result. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. An apparatus comprising at least one processor and at least one machine-accessible medium coupled to said at least one processor, said at least one processor adapted to perform operations comprising a method of:
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obtaining a first circuit layout design; obtaining a second circuit layout design; generating a first topology graph for said first circuit layout design; generating a second topology graph for said second circuit layout design; comparing said first topology graph and said second topology graph to obtain a comparison result, wherein said comparison result comprises at least a first matched topology graph node pair and a second matched topology graph node pair connected via a topology graph line pair, said topology graph line pair having a pair of lengths and a pair of widths, wherein said method further comprises; comparing said pair of lengths to a length sensitivity parameter; and comparing said pair of widths to a width sensitivity parameter; and
reporting said comparison result. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24)
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25. An apparatus comprising:
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a topology graph generator to produce a first topology graph from a first circuit layout design and to produce a second topology graph from a second circuit layout design; and a comparator coupled to said topology graph generator, said comparator to receive said first topology graph and said second topology graph from said topology graph generator, said comparator to compare said first topology graph and said second topology graph to obtain a comparison result, wherein said comparison result comprises at least a first matched topology graph node pair and a second matched topology graph node pair connected via a topology graph line pair, said topology graph line pair having a pair of lengths and a pair of widths, wherein said comparator further; compares said pair of lengths to a length sensitivity parameter; and compares said pair of widths to a width sensitivity parameter. - View Dependent Claims (26, 27, 28, 29, 30, 31, 32)
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Specification