Fabrication of semiconductor interconnect structures

• US 7,172,497 B2
• Filed: 10/03/2002
• Issued: 02/06/2007
• Est. Priority Date: 01/05/2001
• Status: Expired due to Term

• Current Assignee: Novellus Systems Incorporated (Lam Research Corporation)
• Original Assignee: ASM NuTool, Inc. (ASM International NV)
• Inventors: Basol, Bulent M., Talieh, Homayoun
• Primary Examiner(s): Eley; Timothy V.
• Application Number:
  US10/264,726
• Publication Number:
  US 20030032373A1
• Time in Patent Office: 1,587 Days
• Field of Search: 451/36, 451/37, 451/41, 451/54, 451/57, 451/59, 451/63, 451/65, 451/66, 451/67, 451/331, 451/339, 156/345.12, 204/198, 204/241, 204/269, 204/270, 216/38, 216 88- 90, 216/108, 216/109, 438690-693
• US Class Current: 451/54
• CPC Class Codes: B24B 37/042 operating processes therefor
• CPC Class Codes: B24B 37/046 using electric current
• CPC Class Codes: B24B 49/16 taking regard of the load
• CPC Class Codes: C25D 17/001 Apparatus specially adapted for electrolytic coating of wafers, e.g. semiconductors or solar cells
• CPC Class Codes: C25D 5/06 Brush or pad plating
• CPC Class Codes: C25D 7/123 Semiconductors first coated with a seed layer or a conductive layer
• CPC Class Codes: H01L 21/67173 in-line arrangement
• CPC Class Codes: H01L 21/67207 comprising a chamber adapted to a particular process
• CPC Class Codes: H01L 21/67219 comprising at least one polishing chamber polishing apparatuses B24B
• CPC Class Codes: H01L 21/6723 comprising at least one plating chamber electroless plating apparatuses C23C, electroplating apparatuses C25D
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation

Abstract

A system and a method of forming copper interconnect structures in a surface of a wafer is provided. The method includes a step of performing a planar electroplating process in an electrochemical mechanical deposition station for filling copper material into a plurality of cavities formed in the surface of the wafer. The electroplating continues until a planar layer of copper with a predetermined thickness is formed on the surface of the wafer. In a following chemical mechanical polishing step the planar layer is removed until the copper remains in the cavities, insulated from one another by exposed regions of the dielectric layer.

Claims

1. A method of fabricating conductive structures in a plurality of cavities formed in a surface of a substrate, wherein the surface and the cavities are coated with a conducting film, and wherein the conducting film comprises a barrier layer, the method comprising the steps of:

performing in a first station an electrochemical mechanical deposition (ECMD) process for filling a conductive material into the plurality of cavities until a planar layer of conductive material with a predetermined thickness is formed on the surface of the substrate;

moving the substrate to a second station after performing the ECMD process; and

applying a chemical mechanical polishing process in the second station to polish the conductive material and the conducting film off the surface of the substrate.

2. The method of claim 1, wherein the applying step comprises a first chemical mechanical process step to remove the planar layer until the barrier layer is exposed on the surface and the conductive material remains in the cavities.

3. The method of claim 2, wherein the applying step further comprises a second chemical mechanical process step to remove the barrier layer from the surface while leaving the conductive material in the cavities, isolated from one another, the second chemical mechanical process step being performed after the first chemical mechanical process step.

4. The method of claim 3, wherein the second chemical mechanical polishing process step uses a non-abrasive polishing pad and a polishing slurry.

5. The method of claim 2, wherein the planar layer has a thickness that is less than ¾

of a depth of the cavities.

6. The method of claim 2, wherein the first chemical mechanical polishing process step uses a fixed abrasive polishing pad and a polishing slurry.

7. The method of claim 1, wherein the applying step removes the planar conductive layer and the barrier layer on the surface of the substrate in a single step so that the conductive material remains in the cavities, isolated from one another.

8. The method of claim 7, wherein the predetermined thickness of the planar layer is less than 2000 Angstroms.

9. The method of claim 7, further comprising polishing the surface of the substrate so as to remove a predetermined thickness of an insulator layer on the substrate surface.

10. The method of claim 1, further comprising performing an anneal step for annealing the conductive material prior to chemical mechanical polishing.

11. The method of claim 1, further comprising performing an anneal step for annealing the conductive material prior to chemical mechanical polishing and then subsequent to chemical mechanical polishing.

12. The method of claim 1, further comprising performing an anneal step for annealing the conductive material subsequent to chemical mechanical polishing.

13. The method of claim 1, wherein performing in a first station an electrochemical mechanical deposition (ECMD) process comprises using a pad to maintain the planarity of the surface.

14. A method of fabricating conductive structures in a plurality of cavities formed in a surface of a substrate, wherein the surface and the cavities are coated with a conducting film, and wherein the conducting film comprises a barrier layer, the method comprising the steps of:

performing an electrochemical mechanical deposition (ECMD) process for filling a conductive material into the plurality of cavities until a planar layer of conductive material with a predetermined thickness is formed on the surface of the substrate; and

applying a two step chemical mechanical polishing process to polish the conductive material and the conducting film off the surface of the substrate, wherein a first step of the polishing process removes the conductive material on the surface of the substrate and then a second step of the polishing process removes the barrier layer on the surface so that the conductive material remains in the cavities, isolated from one another.

15. A method of fabricating conductive structures in a plurality of cavities formed in a surface of a substrate, wherein the surface and the cavities are coated with a conducting film, and wherein the conducting film comprises a barrier layer, the method comprising the steps of:

performing in a first station an electrochemical mechanical deposition process for filling a conductive material into the plurality of cavities until a planar layer of conductive material with a predetermined thickness is formed on the surface of the substrate;

moving the substrate into a second station after performing the electrochemical mechanical deposition process; and

applying in a second station a single step chemical mechanical polishing process to polish the conductive material and the conductive film off the surface of the substrate so that the conductive material remains in the cavities, isolated from one another.

16. A method of manufacturing a semiconductor device comprising:

electroplating in a first station a planar layer of conductive material onto a substrate using an electrochemical mechanical deposition (ECMD) process;

moving the substrate into a second station after electroplating; and

performing in a second station a chemical mechanical process to polish the conductive layer.