Method and structure for forming an integrated spatial light modulator

• US 7,172,921 B2
• Filed: 01/03/2005
• Issued: 02/06/2007
• Est. Priority Date: 01/03/2005
• Status: Active Grant

• Current Assignee: Miradia Inc. (Walsin Lihwa Corporation)
• Original Assignee: Miradia Inc. (Walsin Lihwa Corporation)
• Inventors: Yang, Xiao, Chen, Dongmin
• Primary Examiner(s): Whitehead, Jr.; Carl
• Assistant Examiner(s): Dolan; Jennifer M
• Application Number:
  US11/028,946
• Publication Number:
  US 20060148121A1
• Time in Patent Office: 764 Days
• Field of Search: 438/27, 438/29, 438/57, 438/64, 438/65, 438/66, 438/73, 257/428, 257/444, 359/291, 359/315
• US Class Current: 438/66
• CPC Class Codes: G02B 26/0841 the reflecting element being moved or deformed by electrostatic means

Abstract

A method of fabricating an integrated spatial light modulator. The method includes providing a first substrate including a bonding surface, processing a device substrate to form at least an electrode layer, the electrode layer including a plurality of electrodes, and depositing a standoff layer on the electrode layer. The method further includes forming standoff structures from the standoff layer and joining the bonding surface of the first substrate to the standoff structures on the device substrate. In a particular embodiment, the method further includes, after the step of depositing a standoff layer, performing chemical mechanical polishing of the standoff layer to planarize an upper surface of the standoff layer.

Claims

1. A method of fabricating an integrated spatial light modulator, the method comprising:

providing a first substrate including a bonding surface;

processing a device substrate to form at least an electrode layer, the electrode layer including a plurality of electrodes;

depositing a standoff layer on the electrode layer;

forming standoff structures from the standoff layer, wherein the standoff structures are provided in a spatial manner as an array including a plurality of first standoff regions arranged in strips and a plurality of second standoff regions arranged in strips, the second standoff regions intersecting the first standoff regions to form the array;

joining the bonding surface of the first substrate to the standoff structures on the device substrate;

thinning the first substrate;

patterning the first substrate to form a mask; and

forming a plurality of moveable structures from the first substrate, at least one of the moveable structures aligned with at least one of the plurality of electrodes and adapted to rotate with respect to the standoff structures.

2. The method of claim 1 further comprising, after the step of depositing a standoff layer, performing chemical mechanical polishing of the standoff layer to planarize an upper surface of the standoff layer.

3. The method of claim 1 wherein the first substrate is a silicon on insulator substrate.

4. The method of claim 1 wherein the standoff layer is fabricated from silicon oxide.

5. The method of claim 4 wherein the standoff structures are thermally insulating.

6. The method of claim 4 wherein the standoff structures are electrically insulating.

7. The method of claim 4 wherein the standoff layer is deposited using a low temperature deposition process.

8. The method of claim 7 wherein the low temperature deposition process is a deposition process performed at a temperature of less than 400°

C.

9. The method of claim 7 wherein the device substrate comprises CMOS circuitry.

10. The method of claim 1 wherein the standoff structures have a height of between 0.5 μ

m and 2.5 μ

m.

11. The method of claim 1 wherein the step of forming comprises etching the standoff layer to form the standoff structures.

12. The method of claim 1 wherein the step of joining is performed using an alignment process with a tolerance requirement of less than 1 cm.

13. The method of claim 12 wherein the step of joining comprises forming a covalent bond at room temperature.

14. The method of claim 13 wherein the step of joining comprises a plasma activation process and a room temperature covalent bonding process.

15. A method of fabricating an integrated spatial light modulator, the method comprising:

providing a first substrate including a bonding surface;

providing a second substrate including a plurality of electrodes;

depositing a standoff layer on the second substrate;

forming standoff structures from the standoff layer, wherein forming standoff structures comprises etching the standoff layer to form an array pattern including a plurality of first standoff regions arranged in strips and a plurality of second standoff regions arranged in strips, the second standoff regions intersecting the first standoff regions to form the array pattern;

joining the bonding surface of the first substrate to the standoff structures on the second substrate;

thinning the first substrate;

patterning the first substrate to form a mask; and

forming a plurality of moveable structures from the first substrate, at least one of the moveable structures aligned with at least one of the plurality of electrodes.

16. The method of claim 15 wherein the step of thinning the first substrate comprises removing a first silicon layer and a buried oxide layer to expose a second semi-transparent silicon layer.

17. The method of claim 16 wherein the step of patterning the first substrate to form an etch mask comprises imaging the second substrate through the second semi-transparent silicon layer to align the at least one of the plurality of moveable structures with at least one of the plurality of electrodes.

18. An array of integrated spatial light modulators comprising:

an electrode layer coupled to a device substrate, the electrode layer including a plurality of electrodes and at least one alignment mark;

a three-dimensional standoff structure, the standoff structures having side regions, bottom regions coupled to the device substrate, and top regions opposite the bottom regions, wherein the top regions are disposed in an array pattern including a plurality of first standoff regions arranged in strips and a plurality of second standoff regions arranged in strips, the second standoff regions intersecting the first standoff regions to form the array pattern; and

a semi-transparent silicon layer coupled to the top regions of the standoff structure, the semi-transparent silicon layer comprising;

a hinge support region coupled to the top regions of the standoff structure;

a plurality of hinges coupled to the hinge support regions; and

a plurality of moveable members aligned with respect to the at least one alignment mark by imaging the at least one alignment mark through the semi-transparent silicon layer.

19. The array of integrated spatial light modulators of claim 18 wherein the standoff structure is fabricated from a layer selected from the group consisting of silicon oxide, silicon nitride, and silicon oxynitride.

20. The array of integrated spatial light modulators of claim 19 wherein the layer is polished using a chemical mechanical polishing process after deposition.