On-chip inductors

• US 7,173,318 B2
• Filed: 01/02/2001
• Issued: 02/06/2007
• Est. Priority Date: 07/28/2000
• Status: Expired due to Term

• Current Assignee: Newport Fab, LLC (Tower Semiconductor Limited)
• Original Assignee: Newport Fab, LLC (Tower Semiconductor Limited)
• Inventors: Howard, David, Liu, Q Z, Zhao, Bin
• Primary Examiner(s): Nadav, Ori
• Application Number:
  US09/754,806
• Publication Number:
  US 20020011646A1
• Time in Patent Office: 2,226 Days
• Field of Search: 257/531, 257/516, 438/210, 438/329
• US Class Current: 257/531
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 28/10 Inductors

Abstract

Method for fabrication of on-chip inductors and related structure are disclosed. According to one embodiment, inductors are formed by patterning conductors within a certain dielectric layer in a semiconductor die. Thereafter, the entire dielectric layer in the semiconductor die is subjected to a blanket implantation or sputtering of high permeability material. According to another embodiment, a first area in a semiconductor die is covered, for example, with photoresist. A second area in the semiconductor die includes a patterned conductor which is to be used as an inductor. The patterned conductor is also covered, for example, with photoresist. The second area, excluding the covered patterned conductor, is subjected to implantation or sputtering of high permeability material. According to yet another embodiment, a first area of a semiconductor die is covered, for example, with photoresist. A second area in the semiconductor area includes a patterned conductor which is to be used as an inductor. This second area, including the patterned conductor, is subjected to implantation or sputtering of high permeability material. The implantation or sputtering of high permeability materials result in the inductors having much higher inductance values than they would otherwise have.

Claims

1. A structure in a semiconductor chip, said structure comprising:

a first area of a dielectric, said first area of said dielectric having a first permeability;

a second area of said dielectric, said second area of said dielectric having a second permeability, said second permeability being higher than said first permeability;

a permeability conversion material interspersed within said second area of said dielectric, said permeability conversion material having a third permeability, said third permeability being greater than said first and said second permeabilities;

a conductor patterned in said second area of said dielectric, said permeability conversion material not being situated underneath said conductor;

wherein said dielectric is not situated underneath said conductor and not situated over said conductor, wherein said first area of said dielectric is not situated underneath said second area of said dielectric and not situated over said second area of said dielectric, wherein said dielectric is a low-k dielectric, wherein said permeability conversion material is selected from the group consisting of nickel, iron, nickel-iron alloy, and magnetic oxide, wherein said conductor is selected from the group consisting of copper, aluminum, and copper-aluminum alloy, and wherein said permeability conversion material is interspersed in said second area of said dielectric by ion implantation, wherein said first area of said dielectric, said second area of said dielectric, and said conductor have a same thickness.

2. The structure of claim 1 wherein said dielectric is silicon dioxide.

3. The structure of claim 1 wherein said conductor is patterned as a square spiral.

4. A structure in a semiconductor chip, said structure comprising:

a dielectric having a first permeability;

a permeability conversion material having a second permeability, said permeability conversion material being interspersed within said dielectric, wherein said second permeability is greater than said first permeability;

an inductor comprising a conductor patterned within said dielectric, said conductor having first and second terminals, said first and second terminals of said conductor being respectively first and second terminals of said inductor, said permeability conversion material not being situated underneath said inductor, said dielectric not being situated underneath and not being situated over said inductor;

wherein said permeability conversion material comprises metal ions, wherein said conductor comprises a plurality of metal turns, wherein said plurality of metal turns are not situated underneath said dielectric and not situated above said dielectric, wherein said dielectric and said plurality of metal turns of said conductor have a same thickness.

5. The structure of claim 4 wherein said dielectric is silicon dioxide.

6. The structure of claim 4 wherein said dielectric is a low-k dielectric.

7. The structure of claim 4 wherein said permeability conversion material is selected from the group consisting of nickel, iron, nickel-iron alloy, and magnetic oxide.

8. The structure of claim 4 wherein said conductor is selected from the group consisting of copper, aluminum, and copper-aluminum alloy.

9. The structure of claim 4 wherein said conductor is patterned as a square spiral.

10. A semiconductor chip comprising:

a first dielectric area of a dielectric having a first permeability;

a second dielectric area of said dielectric having a permeability conversion material interspersed therein such that a permeability of said second dielectric area is higher than said first permeability;

an inductor patterned in said second dielectric area, said inductor having first and second connection terminals, said first and second connection terminals being capable of providing connection to a device fabricated in said first dielectric area of said semiconductor chip, said permeability conversion material not being situated underneath said inductor;

wherein said dielectric is not situated underneath said inductor and not situated over said inductor, wherein said first dielectric area of said dielectric is not situated underneath said second dielectric area of said dielectric and not situated over said second dielectric area of said dielectric, wherein said permeability conversion material is interspersed in said second dielectric area of said dielectric by ion sputtering, wherein said first dielectric area, said second dielectric area, and said inductor have a same thickness.

11. The semiconductor chip of claim 10 wherein said permeability conversion material is interspersed in said second dielectric area when said first dielectric area is covered with photoresist.

12. The semiconductor chip of claim 10 wherein said first dielectric area comprises silicon dioxide.

13. The semiconductor chip claim 10 wherein said first dielectric area comprises a low-k dielectric.

14. The semiconductor chip of claim 10 wherein said second dielectric area comprises silicon dioxide.

15. The semiconductor chip of claim 10 wherein said second dielectric area comprises a low-k dielectric.

16. The semiconductor chip of claim 10 wherein said permeability conversion material is selected from the group consisting of nickel, iron, nickel-iron alloy, and magnetic oxide.

17. The semiconductor chip of claim 10 wherein said permeability conversion material is interspersed in said second dielectric area by ion implantation.

18. The semiconductor chip of claim 10 wherein said inductor comprises material selected from the group consisting of copper, aluminum, and copper-aluminum alloy.

19. The semiconductor clip of claim 10 wherein said inductor is patterned as a square spiral.

20. The semiconductor chip of claim 18 wherein said permeability conversion material is selected from the group consisting of nickel, iron, nickel-iron alloy, and magnetic oxide.