Timing signal generating circuit having simple configuration with low supply voltage and generating timing signals with high accuracy

• US 7,173,466 B2
• Filed: 01/22/2003
• Issued: 02/06/2007
• Est. Priority Date: 02/01/2002
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Tamura, Hirotaka, Chiba, Takaya
• Primary Examiner(s): NGUYEN, LONG T
• Application Number:
  US10/347,913
• Publication Number:
  US 20030146780A1
• Time in Patent Office: 1,476 Days
• Field of Search: 327/237, 327/231, 327/258, 327/259, 327236-239, 327/246, 327/247, 327250-255, 327/361, 327/407, 327/408, 327/308, 327/334, 327/103, 327/156, 327/158, 327/234, 375/354, 375/373, 375374-376, 455/130, 455/260
• US Class Current: 327/231
• CPC Class Codes: H03K 5/13 Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
• CPC Class Codes: H04L 7/0025 interpolation of clock signal
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Abstract

A timing signal generating circuit receives multiphase input signals and generates a signal having a phase intermediate therebetween, and weighting is applied to the multi-phase input signals by using a variable impedance circuit. The timing signal generating circuit (receiver circuit) can operate with a low supply voltage, is simple in configuration, and can generate timing signals with high accuracy.

Claims

1. A timing signal generating circuit which receives multi-phase input signals via a plurality of input buffers and generates a signal having a phase intermediate therebetween, wherein weighting is applied to said multi-phase input signals by using a variable impedance circuit, each of said input buffers comprising a plurality of stages of electronic elements between a high potential power supply line and a low potential power supply line, said variable impedance circuit comprising a plurality of variable impedance units one for each of said multi-phase input signals, each of said variable impedance units including at least one transistor without providing vertically stacked transistors between the high potential power supply line and the low potential power supply line, and without increasing a number of stages of electronic elements between the high potential power supply line and the low potential power supply line of said input buffers,

wherein the at least one transistor of each of said variable impedance units includes a first, a second, and a control electrode, said each input signal is received at said first electrode and output at said second electrode, and impedance is controlled by controlling a voltage applied to said control electrode,

wherein each of said variable impedance units comprises a plurality of variable impedance parts that include said at least one transistor, and wherein said variable impedance parts are arranged to form a plurality of variable impedance groups.

2. The timing signal generating circuit as claimed in claim 1, wherein said multi-phase input signals are clocks of three or more phases.

3. The timing signal generating circuit as claimed in claim 2, wherein said multi-phase input signals are four-phase clocks.

4. The timing signal generating circuit as claimed in claim 1, wherein each of said variable impedance units comprises a plurality of resistive elements and switching elements parallelly connected in pairs, and impedance is controlled by varying the number of switching elements to be turned on, wherein the switching elements include the at least one transistor.

5. The timing signal generating circuit as claimed in claim 1, wherein each of said variable impedance units comprises a plurality of resistive elements and switching elements serially connected in pairs, and impedance is controlled by controlling the number of switching elements to be turned on, wherein the switching elements include the at least one transistor.

6. The timing signal generating circuit as claimed in claim 1, wherein said at least one transistor is a MOS transistor.

7. The timing signal generating circuit as claimed in claim 1, wherein said at least one transistor is a transistor pair consisting of a PMOS transistor and an NMOS transistor connected in parallel.

8. The timing signal generating circuit as claimed in claim 1, further comprising a current-voltage conversion circuit for converting a current control signal into a voltage control signal, and wherein said impedance is controlled by said voltage control signal.

9. The timing signal generating circuit as claimed in claim 1, wherein each of said variable impedance groups applies the same weighting to each of said multi-phase input signals applied thereto.

10. The timing signal generating circuit as claimed in claim 1, further comprising output buffers which are placed at an output stage of said timing signal generating circuit.

11. The timing signal generating circuit as claimed in claim 10, wherein said buffers are differential buffers.

12. A timing signal generating circuit which receives multi-phase input signals via a plurality of input buffers and generates multi-phase output signals, wherein weighting is applied to said multi-phase input signals by using a variable impedance circuit, each of said input buffers comprising a plurality of stages of electronic elements between a high potential power supply line and a low potential power supply line, said variable impedance circuit comprising a plurality of variable impedance units one for each of said multi-phase input signals, each of said variable impedance units including a plurality of variable impedance parts having at least one transistor without providing vertically stacked transistors between the high potential power supply line and the low potential power supply line, and without increasing the number of stages of said electronic elements between the high potential power supply line and the low potential power supply line of said input buffers, wherein said variable impedance parts are arranged to form a plurality of variable impedance groups one for each of said multi-phase input signals and each of said variable impedance groups outputs said multi-phase output signals of the same number of phases as said multi-phase input signals, each of said variable impedance groups applying the same weighting to each of said multi-phase input signals applied thereto.

13. The timing signal generating circuit as claimed in claim 12, wherein said input signals are four-phase clocks, and wherein four variable impedance groups are provided and said variable impedance groups output four-phase signals that are spaced 90°

apart in phase as said multi-phase output signals.

14. A timing signal generating circuit which receives multi-phase input signals via a plurality of input buffers and generates a signal having a phase intermediate therebetween,

wherein weighting is applied to said multi-phase input signals by using a variable impedance circuit, each of said input buffers comprising a plurality of stages of electronic elements between a high potential power supply line and a low potential power supply line, said variable impedance circuit comprising a plurality of variable impedance units one for each of said multi-phase input signals, each of said variable impedance units including at least one transistor without providing vertically stacked transistors between the high potential power supply line and the low potential power supply line, and without increasing a number of stages of electronic elements between the high potential power supply line and the low potential power supply line of said input buffers,

wherein the at least one transistor of each of said variable impedance units includes a first, a second, and a control electrode, said each input signal is received at said control electrode and output at said second electrode, and impedance is controlled by controlling a voltage applied to said first electrode,

wherein each of said variable impedance units comprises a plurality of variable impedance parts that include said at least one transistor, and wherein said variable impedance parts are arranged to form a plurality of variable impedance groups.

15. The timing signal generating circuit as claimed in claim 14, wherein said at least one transistor is a MOS transistor.

16. The timing signal generating circuit as claimed in claim 14, wherein said at least one transistor is a transistor pair consisting of a PMOS transistor and an NMOS transistor connected in parallel.

17. The timing signal generating circuit as claimed in claim 14, wherein each of said variable impedance groups applies the same weighting to each of said multi-phase input signals applied thereto.

18. The timing signal generating circuit as claimed in claim 14, further comprising output buffers which are placed at an output stage of said timing signal generating circuit.

19. The timing signal generating circuit as claimed in claim 18, wherein said buffers are differential buffers.

20. A receiver circuit comprising:

a data detection-discrimination circuit for detecting and discriminating data carried in an input signal;

a changing point detection-discrimination circuit for detecting and discriminating a changing point appearing in said input signal;

a phase comparator circuit for receiving outputs from said data detection-discrimination circuit and said changing point detection-discrimination circuit, and for comparing the phases of said outputs; and

a clock signal generating circuit for receiving an output from said phase comparator circuit, wherein

said clock signal generating circuit is a timing signal generating circuit which receives multi-phase input signals via a plurality of input buffers and generates at least one signal having a phase intermediate therebetween, wherein weighting is applied to said multi-phase input signals by using a variable impedance circuit, each of said input buffers comprising a plurality of stages of electronic elements between a high potential power supply line and a low potential power supply line, said variable impedance circuit comprising a plurality of variable impedance units one for each of said multi-phase input signals, each of said variable impedance units including at least one transistor without providing vertically stacked transistors between the high potential power supply line and the low potential power supply line, and without increasing a number of stages of electronic elements between the high potential power supply line and the low potential power supply line of said input buffers,

wherein said at least one transistor of each of said variable impedance units has a first, a second, and a control electrode, said each input signal is received at said first electrode and output at said second electrode, and impedance is controlled by controlling a voltage applied to said control electrode,

wherein each of said variable impedance units comprises a plurality of variable impedance parts, each including said at least one transistor, and wherein said variable impedance parts are arranged to form a plurality of variable impedance groups.

21. The receiver circuit as claimed in claim 20, wherein said multi-phase input signals are clocks of three or more phases.

22. The receiver circuit as claimed in claim 21, wherein said multi-phase input signals are four-phase clocks.

23. The receiver circuit as claimed in claim 20, wherein each of said variable impedance units comprises a plurality of resistive elements and switching elements parallelly connected in pairs, and impedance is controlled by varying the number of switching elements to be turned on, wherein said switching elements include said at least one transistor.

24. The receiver circuit as claimed in claim 20, wherein each of said variable impedance units comprises a plurality of resistive elements and switching elements serially connected in pairs, and impedance is controlled by controlling the number of switching elements to be turned on, wherein said switching elements include said at least one transistor.

25. The receiver circuit as claimed in claim 20, wherein said at least one transistor is a MOS transistor.

26. The receiver circuit as claimed in claim 20, wherein said at least one transistor is a transistor pair consisting of a PMOS transistor and an NMOS transistor connected in parallel.

27. The receiver circuit as claimed in claim 20, wherein said timing signal generating circuit further comprises a current-voltage conversion circuit for converting a current control signal into a voltage control signal, and wherein said impedance is controlled by said voltage control signal.

28. The receiver circuit as claimed in claim 20, wherein each of said variable impedance groups applies the same weighting to each of said multi-phase input signals applied thereto.

29. The receiver circuit as claimed in claim 28, wherein said variable impedance groups are equal in number to said multi-phase input signals, and said variable impedance groups output multi-phase output signals of the same number of phases as said multi-phase input signals, and said at least one signal is comprised of said multi-phase output signals.

30. The receiver circuit as claimed in claim 29, wherein said input signals are four-phase clocks, and wherein four variable impedance groups are provided and said variable impedance groups output four-phase signals that are spaced 90°

apart in phase as said multi-phase output signals.

31. The receiver circuit as claimed in claim 20, wherein said timing signal generating circuit further comprises output buffers which are placed at an output stage of said timing signal generating circuit.

32. The receiver circuit as claimed in claim 31, wherein said buffers are differential buffers.

33. The receiver circuit as claimed in claim 20, wherein said clock signal generating circuit generates at least one signal in addition to said at least one signal such that at least two signals are generated and supplies one of said at least two signals as a first internal clock to said data detection-discrimination circuit and another of said at least two signals as a second internal clock to said changing point detection-discrimination circuit.

34. A receiver circuit comprising:

a data detection-discrimination circuit for detecting and discriminating data carried in an input signal;

a changing point detection-discrimination circuit for detecting and discriminating a changing point appearing in said input signal;

a phase comparator circuit for receiving outputs from said data detection-discrimination circuit and said changing point detection-discrimination circuit, and for comparing the phases of said outputs; and

a clock signal generating circuit for receiving an output from said phase comparator circuit, wherein

said clock signal generating circuit is a timing signal generating circuit which receives multi-phase input signals via a plurality of input buffers and generates at least one signal having a phase intermediate therebetween wherein weighting is applied to said multi-phase input signals by using a variable impedance circuit, each of said input buffers comprising a plurality of stages of electronic elements between a high potential power supply line and a low potential power supply line, said variable impedance circuit comprising a plurality of variable impedance units one for each of said multi-phase input signals, each of said variable impedance units including at least one transistor without providing vertically stacked transistors between the high potential power supply line and the low potential power supply line, and without increasing a number of stages of electronic elements between the high potential power supply line and the low potential power supply line of said input buffers,

wherein said at least one transistor of each of said variable impedance units has a first, a second, and a control electrode, said each input signal is received at said control electrode and output at said second electrode, and impedance is controlled by controlling a voltage applied to said first electrode,

wherein each of said variable impedance units comprises a plurality of variable impedance parts, each including said at least one transistor, and wherein said variable impedance parts are arranged to form a plurality of variable impedance groups.

35. The receiver circuit as claimed in claim 34, wherein said at least one transistor is a MOS transistor.

36. The receiver circuit as claimed in claim 34, wherein said at least one transistor is a transistor pair consisting of a PMOS transistor and an NMOS transistor connected in parallel.

37. The receiver circuit as claimed in claim 34, wherein each of said variable impedance groups applies the same weighting to each of said multi-phase input signals applied thereto.

38. The receiver circuit as claimed in claim 37, wherein said variable impedance groups are equal in number to said multi-phase input signals, and said variable impedance groups output multi-phase output signals of the same number of phases as said multi-phase input signals received via said input buffers, and said at least one signal is comprised of said multi-phase output signals.

39. The receiver circuit as claimed in claim 38, wherein said input signals are four-phase clocks, and wherein four variable impedance groups are provided and said variable impedance groups output four-phase signals that are spaced 90°

apart in phase as said multi-phase output signals.

40. The receiver circuit as claimed in claim 34, wherein said timing signal generating circuit further comprises output buffers which are placed at an output stage of said timing signal generating circuit.

41. The receiver circuit as claimed in claim 40, wherein said buffers are differential buffers.