Signal detector
First Claim
1. A signal detector comprising:
- a plurality of signal transfer transistors arranged in the form of a matrix;
signal detection means connected to a first terminal of each said signal transfer transistor;
a data line connected to a second terminal of each said signal transfer transistor;
a control line connected to a control terminal of each said signal transfer transistor;
a control line driving circuit for driving said control line;
a plurality of switching transistors configured to couple a plurality of said data lines to a plurality of data read lines, respectively; and
a switch driving circuit for driving said plurality of switching transistors at substantially the same time to enable data from said plurality of data lines to be read out in parallel to said plurality of data read lines, said switch driving circuit for providing said read data in parallel to a circuit for comparing said read data with reference data.
1 Assignment
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Accused Products
Abstract
A signal detector capable of linearly reading data at a high speed is obtained. This signal detector comprises a plurality of signal transfer transistors arranged in the form of a matrix, signal detection means connected to a first terminal of each signal transfer transistor, a data line connected to a second terminal of each signal transfer transistor, a control line connected to the gate of each signal transfer transistor, a gate line driving circuit for driving the control line, data read lines connected to a plurality of prescribed data lines through switching transistors respectively, and a switch driving circuit for driving the switching transistors corresponding to the aforementioned plurality of prescribed data lines substantially at the same timing. Thus, a plurality of prescribed data are simultaneously read for enabling linear data reading and increasing the speed of data reading.
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Citations
21 Claims
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1. A signal detector comprising:
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a plurality of signal transfer transistors arranged in the form of a matrix; signal detection means connected to a first terminal of each said signal transfer transistor; a data line connected to a second terminal of each said signal transfer transistor; a control line connected to a control terminal of each said signal transfer transistor; a control line driving circuit for driving said control line; a plurality of switching transistors configured to couple a plurality of said data lines to a plurality of data read lines, respectively; and a switch driving circuit for driving said plurality of switching transistors at substantially the same time to enable data from said plurality of data lines to be read out in parallel to said plurality of data read lines, said switch driving circuit for providing said read data in parallel to a circuit for comparing said read data with reference data. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 17, 18)
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10. The signal detector according to clam 1, wherein
said control line driving circuit includes a shift register.
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19. A signal detector comprising:
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a plurality of transfer transistors arranged in the form of a matrix; means connected to the source of each said transfer transistor for detecting the pressure of a surface; a data line connected to the drain of each said transfer transistor; a gate line connected to the gate of each said transfer transistor; a gate line driving circuit for driving said gate line; a plurality of switching transistors configured to couple a plurality of said data lines to a plurality of data read lines, respectively; and a single switch driving circuit for driving the gates of said plurality of switching transistors to enable data to be read out in parallel from said plurality of data lines to said plurality of data read lines, said switch driving circuit for providing said read data in parallel to a circuit for comparing said read data with reference data. - View Dependent Claims (20)
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21. A signal detector comprising:
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a plurality of signal transfer transistors arranged in the form of a matrix; signal detection means connected to a first terminal of each said signal transfer transistor; a data line connected to a second terminal of each said signal transfer transistor; a control line connected to a control terminal of each said signal transfer transistor; a control line driving circuit for driving said control line; a plurality of switching transistors configured to couple a plurality of said data lines to a plurality of data read lines, respectively; and a switch driving circuit for driving said plurality of switching transistors at substantially the same time to enable data from said plurality of data lines to be read out in parallel to said plurality of data read lines, wherein the switch driving circuit simultaneously provides a plurality of read data to a circuit for comparing said read data with reference data.
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Specification