Complex-IF digital receiver

• US 7,173,980 B2
• Filed: 09/20/2002
• Issued: 02/06/2007
• Est. Priority Date: 09/20/2002
• Status: Expired due to Term

• Current Assignee: Axiom Microdevices Incorporated (Skyworks Solutions Incorporated)
• Original Assignee: Ditrans IP, Inc.
• Inventors: Masenten, Wesley K., Hoo, Keith Soo, Stubberud, Peter, Dinh, Thang Victor, Dagher, Elias
• Primary Examiner(s): Fan, Chieh M.
• Assistant Examiner(s): Nguyen, Dung X.
• Application Number:
  US10/251,663
• Publication Number:
  US 20040057534A1
• Time in Patent Office: 1,600 Days
• Field of Search: 375/316, 375/261, 375/324, 375/328, 375/332, 375/350
• US Class Current: 375/316
• CPC Class Codes: H03M 3/3287 the dither being at least partially dependent on the input signal
• CPC Class Codes: H03M 3/43 the quantiser being a single bit one
• CPC Class Codes: H03M 3/454 with distributed feedback, i.e. with feedback paths from the quantiser output to more than one filter stage

Abstract

An improved complex-IF digital receiver has various improvements. The improved complex-IF digital receiver, for single or dual band applications, preferably synchronizes all of the signals to each other, which may be an integer multiple of each other. For example, the decimation filter, delta-sigma modulator, sensitivity DAC, and other circuits in the receiver can be synchronized. The delta-sigma modulator preferably includes a comparator whose input is coupled to a sensitivity DAC or synchronous dithering circuit. Ideally, the sensitivity DAC forces the comparator to trigger at every clock cycle and reduces the effect of hysteresis and offset at the input of the comparator. The receiver includes a translation circuit that translates an intermediate frequency signal to baseband, where the translation circuit preferably operates a translation ratio that is a multiple of 4.

Claims

1. A receiver comprising:

an in-phase mixer configure to translate an incoming signal to an in-phase intermediate frequency signal;

an in-phase delta-sigma modulator configured to convert the in-phase intermediate frequency signal into an in-phase digital signal at a predetermined sampling rate;

an in-phase decimation filter configured to decimate the in-phase digital signal;

a quadrature mixer configured to translate an incoming signal to an quadrature intermediate frequency signal;

a quadrature delta-sigma modulator configured to convert the quadrature intermediate frequency signal into a quadrature digital signal at a predetermined sampling rate;

wherein the quadrature delta-sigma modulator is configured to operate independent of the output of the in-phase delta-sigma modulator and the in-phase delta-sigma modulator is configured to operate independent of the output of the quadrature delta-sigma modulator;

a quadrature decimation filter configured to decimate the quadrature digital signal;

a translation circuit configured to translate the decimated in-phase and quadrature digital signals to in-phase and quadrature baseband digital signals; and

a voltage controlled oscillator;

wherein each of the in-phase and quadrature mixers translates the incoming signal by a local oscillator frequency of f_LO derived from the voltage controlled oscillator; and

the sampling rate of each of the in-phase and quadrature delta-sigma modulators is derived from the voltage controlled oscillator and equal to an integer sub-multiple of f_LO; and

wherein each of the in-phase and quadrature intermediate frequency signals has an intermediate frequency equal to f_LO divided by an integer that is a function of a decimation ratio of the each of the in-phase and quadrature decimation filters.

2. The receiver of claim 1, further comprises:

an in-phase bandpass filter interfacing the in-phase mixer to the in-phase delta-sigma modulator; and

a quadrature bandpass filter interfacing the quadrature mixer to the quadrature delta-sigma modulator.

3. The receiver of claim 2, wherein each of the in-phase and quadrature bandpass filters comprises a resonator.

4. The receiver of claim 1, wherein the translation circuit has a translation ratio that is a multiple of four.

5. The receiver of claim 1, wherein each of the in-phase and the quadrature decimation filters has a lowpass frequency response.

6. The receiver of claim 1, wherein each of the in-phase and quadrature delta-sigma modulators further comprises:

an amplifier circuit configured to amplify the respective intermediate signal; and

a comparator configured to convert the respective amplified intermediate signal into the respective digital signal at the sampling rate.

7. A receiver comprising:

an in-phase mixer configured to translate an incoming signal to an in-phase intermediate frequency signal;

an in-phase delta-sigma modulator configured to convert the in-phase intermediate frequency signal into an in-phase digital signal at a predetermined sampling rate;

an in-phase decimation filter configured to decimate the in-phase digital signal;

a quadrature mixer configured to translate the incoming signal to a quadrature intermediate frequency signal;

a quadrature delta-sigma modulator configured to convert the quadrature intermediate frequency signal into a quadrature digital signal at the predetermined sampling rate, wherein the quadrature delta-sigma modulator is configured to operate independent of the output of the in-phase delta-sigma modulator and the in-phase delta-sigma modulator is configured to operate independent of the output of the quadrature delta-sigma modulator;

a quadrature decimation filter configured to decimate the quadrature digital signal; and

a translation circuit configured to translate the decimated in-phase and quadrature digital signals to in-phase and quadrature baseband digital signals;

wherein each of the in-phase and quadrature mixers translates the incoming signal by a local oscillator frequency of f_LO set to a value of

$f_{\mathrm{LO}}=\frac{f_{\mathrm{CH}}}{\left[1+{\left(M_D\times <br><br>M_T\right)}^{-1}\right]}$

where f_CH is a center frequency of the incoming signal, M_D is a decimation ratio of each of the in-phase and quadrature decimation filters, and M_T is a translation ratio of the translation circuit.

8. The receiver of claim 7, wherein each of the in-phase and quadrature intermediate frequency signals has an intermediate frequency equal to

$f_{I\; <li></li><br><br>F}=\frac{f_{\mathrm{LO}}}{\left(M_D\times <br><br>M_T\right)}$

where f_IF is the intermediate frequency, M_D is a decimation ratio of each of the in-phase and quadrature decimation filters, and M_T is a translation ratio of the translation circuit.

9. A receiver comprising:

an in-phase mixer configured to translate an incoming signal to an in-phase intermediate frequency signal;

an in-phase delta-sigma modulator configured to convert the in-phase intermediate frequency signal into an in-phase digital signal at a predetermined sampling rate;

an in-phase decimation filter configured to decimate the in-phase digital signal;

a quadrature mixer configured to translate the incoming signal to a quadrature intermediate frequency signal;

a quadrature delta-sigma modulator configured to convert the quadrature intermediate frequency signal into a quadrature digital signal at the predetermined sampling rate, wherein the quadrature delta-sigma modulator is configured to operate independent of the output of the in-phase delta-sigma modulator and the in-phase delta-sigma modulator is configured to operate independent of the output of the quadrature delta-sigma modulator;

a quadrature decimation filter configured to decimate the quadrature digital signal; and

a translation circuit configured to translate the decimated in-phase and quadrature digital signals to in-phase and quadrature baseband digital signals;

wherein each of the in-phase and quadrature mixers translates the incoming signal by a local oscillator frequency of f_LO, and each of the in-phase and quadrature intermediate frequency signals has an intermediate frequency equal to

$f_{I<br><br><br><br>F}=\frac{f_{\mathrm{LO}}}{\left(M_D\times <br><br>M_T\right)}$

where f_IF is the intermediate frequency, M_D is a decimation ratio of each of the in-phase and quadrature decimation filters, and M_T is a translation ratio of the translation circuit.

10. The receiver of claim 9, wherein M_T is a multiple of four.

11. A receiver comprising:

an in-phase mixer configured to translate an incoming signal to an in-phase intermediate frequency signal;

an in-phase delta-sigma modulator configured to convert the in-phase intermediate frequency signal into an in-phase digital signal at a predetermined sampling rate;

an in-phase decimation filter configured to decimate the in-phase digital signal;

a quadrature mixer configured to translate the incoming signal to a quadrature intermediate frequency signal;

a quadrature delta-sigma modulator configured to convert the quadrature intermediate frequency signal into a quadrature digital signal at the predetermined sampling rate, wherein the quadrature delta-sigma modulator is configured to operate independent of the output of the in-phase delta-sigma modulator and the in-phase delta-sigma modulator is configured to operate independent of the output of the quadrature delta-sigma modulator;

a quadrature decimation filter configured to decimate the quadrature digital signal; and

a translation circuit configured to translate the decimated in-phase and quadrature digital signals to in-phase and quadrature baseband digital signals;

wherein each of the in-phase and quadrature delta-sigma modulators further comprises;

an amplifier circuit configured to amplify the respective intermediate signal;

a comparator configured to convert the respective amplified intermediate signal into the respective digital signal at the sampling rate; and

a sensitivity digital-to-analog converter (DAC) circuit configured to output a switching signal to the comparator at a switching rate that is synchronous with the sampling rate.

12. The receiver of claim 11, wherein the switching signal switches between two analog signals at the switching rate.

13. The receiver of claim 12, wherein the sensitivity DAC circuit has a digital input configured to receive a clock signal at the sampling rate and an analog output configured to output the switching signal to the comparator.

14. A receiver comprising:

an in-phase mixer configured to translate an incoming signal to an in-phase intermediate frequency signal;

an in-phase delta-sigma modulator configured to convert the in-phase intermediate frequency signal into an in-phase digital signal at a predetermined sampling rate;

an in-phase decimation filter configured to decimate the in-phase digital signal;

a quadrature mixer configured to translate the incoming signal to a quadrature intermediate frequency signal;

a quadrature delta-sigma modulator configured to convert the quadrature intermediate frequency signal into a quadrature digital signal at the predetermined sampling rate, wherein the quadrature delta-sigma modulator is configured to operate independent of the output of the in-phase delta-sigma modulator and the in-phase delta-sigma modulator is configured to operate independent of the output of the quadrature delta-sigma modulator;

a quadrature decimation filter configured to decimate the quadrature digital signal; and

a translation circuit configured to translate the decimated in-phase and quadrature digital signals to in-phase and quadrature baseband digital signals;

wherein each of the in-phase and quadrature delta-sigma modulators further comprises;

an amplifier circuit configured to amplify the respective intermediate signal;

wherein the amplifier circuit comprises a first amplifier unit and a second amplifier unit, the output from the first amplifier unit being coupled with the input to the second amplifier unit; and

a comparator configured to convert the respective amplified intermediate signal into the respective digital signal at the sampling rate.

15. The receiver of claim 14, wherein the in-phase and quadrature delta-sigma modulators each further comprise:

a first digital-to-analog converter having an input coupled with an output of the comparator, and an output coupled with the input to the first amplifier unit; and

a second digital-to-analog converter having an input coupled with the output of the comparator, and an output coupled with the input to the second amplifier unit.

16. The receiver of claim 15, further comprising:

an in-phase bandpass filter configured to filter an output of the in-phase mixer and output the filtered signal to the input to the first amplifier unit of the in-phase delta-sigma modulator; and

a quadrature bandpass filter configured to filter an output of the quadrature mixer and output the filtered signal to the input to the first amplifier unit of the quadrature delta-sigma modulator.