Complex-IF digital receiver
First Claim
1. A receiver comprising:
- an in-phase mixer configure to translate an incoming signal to an in-phase intermediate frequency signal;
an in-phase delta-sigma modulator configured to convert the in-phase intermediate frequency signal into an in-phase digital signal at a predetermined sampling rate;
an in-phase decimation filter configured to decimate the in-phase digital signal;
a quadrature mixer configured to translate an incoming signal to an quadrature intermediate frequency signal;
a quadrature delta-sigma modulator configured to convert the quadrature intermediate frequency signal into a quadrature digital signal at a predetermined sampling rate;
wherein the quadrature delta-sigma modulator is configured to operate independent of the output of the in-phase delta-sigma modulator and the in-phase delta-sigma modulator is configured to operate independent of the output of the quadrature delta-sigma modulator;
a quadrature decimation filter configured to decimate the quadrature digital signal;
a translation circuit configured to translate the decimated in-phase and quadrature digital signals to in-phase and quadrature baseband digital signals; and
a voltage controlled oscillator;
wherein each of the in-phase and quadrature mixers translates the incoming signal by a local oscillator frequency of fLO derived from the voltage controlled oscillator; and
the sampling rate of each of the in-phase and quadrature delta-sigma modulators is derived from the voltage controlled oscillator and equal to an integer sub-multiple of fLO; and
wherein each of the in-phase and quadrature intermediate frequency signals has an intermediate frequency equal to fLO divided by an integer that is a function of a decimation ratio of the each of the in-phase and quadrature decimation filters.
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Accused Products
Abstract
An improved complex-IF digital receiver has various improvements. The improved complex-IF digital receiver, for single or dual band applications, preferably synchronizes all of the signals to each other, which may be an integer multiple of each other. For example, the decimation filter, delta-sigma modulator, sensitivity DAC, and other circuits in the receiver can be synchronized. The delta-sigma modulator preferably includes a comparator whose input is coupled to a sensitivity DAC or synchronous dithering circuit. Ideally, the sensitivity DAC forces the comparator to trigger at every clock cycle and reduces the effect of hysteresis and offset at the input of the comparator. The receiver includes a translation circuit that translates an intermediate frequency signal to baseband, where the translation circuit preferably operates a translation ratio that is a multiple of 4.
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Citations
16 Claims
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1. A receiver comprising:
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an in-phase mixer configure to translate an incoming signal to an in-phase intermediate frequency signal; an in-phase delta-sigma modulator configured to convert the in-phase intermediate frequency signal into an in-phase digital signal at a predetermined sampling rate; an in-phase decimation filter configured to decimate the in-phase digital signal; a quadrature mixer configured to translate an incoming signal to an quadrature intermediate frequency signal; a quadrature delta-sigma modulator configured to convert the quadrature intermediate frequency signal into a quadrature digital signal at a predetermined sampling rate;
wherein the quadrature delta-sigma modulator is configured to operate independent of the output of the in-phase delta-sigma modulator and the in-phase delta-sigma modulator is configured to operate independent of the output of the quadrature delta-sigma modulator;a quadrature decimation filter configured to decimate the quadrature digital signal; a translation circuit configured to translate the decimated in-phase and quadrature digital signals to in-phase and quadrature baseband digital signals; and a voltage controlled oscillator; wherein each of the in-phase and quadrature mixers translates the incoming signal by a local oscillator frequency of fLO derived from the voltage controlled oscillator; and the sampling rate of each of the in-phase and quadrature delta-sigma modulators is derived from the voltage controlled oscillator and equal to an integer sub-multiple of fLO; and wherein each of the in-phase and quadrature intermediate frequency signals has an intermediate frequency equal to fLO divided by an integer that is a function of a decimation ratio of the each of the in-phase and quadrature decimation filters. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A receiver comprising:
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an in-phase mixer configured to translate an incoming signal to an in-phase intermediate frequency signal; an in-phase delta-sigma modulator configured to convert the in-phase intermediate frequency signal into an in-phase digital signal at a predetermined sampling rate; an in-phase decimation filter configured to decimate the in-phase digital signal; a quadrature mixer configured to translate the incoming signal to a quadrature intermediate frequency signal; a quadrature delta-sigma modulator configured to convert the quadrature intermediate frequency signal into a quadrature digital signal at the predetermined sampling rate, wherein the quadrature delta-sigma modulator is configured to operate independent of the output of the in-phase delta-sigma modulator and the in-phase delta-sigma modulator is configured to operate independent of the output of the quadrature delta-sigma modulator; a quadrature decimation filter configured to decimate the quadrature digital signal; and a translation circuit configured to translate the decimated in-phase and quadrature digital signals to in-phase and quadrature baseband digital signals; wherein each of the in-phase and quadrature mixers translates the incoming signal by a local oscillator frequency of fLO set to a value of where fCH is a center frequency of the incoming signal, MD is a decimation ratio of each of the in-phase and quadrature decimation filters, and MT is a translation ratio of the translation circuit. - View Dependent Claims (8)
where fIF is the intermediate frequency, MD is a decimation ratio of each of the in-phase and quadrature decimation filters, and MT is a translation ratio of the translation circuit.
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9. A receiver comprising:
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an in-phase mixer configured to translate an incoming signal to an in-phase intermediate frequency signal; an in-phase delta-sigma modulator configured to convert the in-phase intermediate frequency signal into an in-phase digital signal at a predetermined sampling rate; an in-phase decimation filter configured to decimate the in-phase digital signal; a quadrature mixer configured to translate the incoming signal to a quadrature intermediate frequency signal; a quadrature delta-sigma modulator configured to convert the quadrature intermediate frequency signal into a quadrature digital signal at the predetermined sampling rate, wherein the quadrature delta-sigma modulator is configured to operate independent of the output of the in-phase delta-sigma modulator and the in-phase delta-sigma modulator is configured to operate independent of the output of the quadrature delta-sigma modulator; a quadrature decimation filter configured to decimate the quadrature digital signal; and a translation circuit configured to translate the decimated in-phase and quadrature digital signals to in-phase and quadrature baseband digital signals; wherein each of the in-phase and quadrature mixers translates the incoming signal by a local oscillator frequency of fLO, and each of the in-phase and quadrature intermediate frequency signals has an intermediate frequency equal to where fIF is the intermediate frequency, MD is a decimation ratio of each of the in-phase and quadrature decimation filters, and MT is a translation ratio of the translation circuit. - View Dependent Claims (10)
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11. A receiver comprising:
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an in-phase mixer configured to translate an incoming signal to an in-phase intermediate frequency signal; an in-phase delta-sigma modulator configured to convert the in-phase intermediate frequency signal into an in-phase digital signal at a predetermined sampling rate; an in-phase decimation filter configured to decimate the in-phase digital signal; a quadrature mixer configured to translate the incoming signal to a quadrature intermediate frequency signal; a quadrature delta-sigma modulator configured to convert the quadrature intermediate frequency signal into a quadrature digital signal at the predetermined sampling rate, wherein the quadrature delta-sigma modulator is configured to operate independent of the output of the in-phase delta-sigma modulator and the in-phase delta-sigma modulator is configured to operate independent of the output of the quadrature delta-sigma modulator; a quadrature decimation filter configured to decimate the quadrature digital signal; and a translation circuit configured to translate the decimated in-phase and quadrature digital signals to in-phase and quadrature baseband digital signals; wherein each of the in-phase and quadrature delta-sigma modulators further comprises; an amplifier circuit configured to amplify the respective intermediate signal; a comparator configured to convert the respective amplified intermediate signal into the respective digital signal at the sampling rate; and a sensitivity digital-to-analog converter (DAC) circuit configured to output a switching signal to the comparator at a switching rate that is synchronous with the sampling rate. - View Dependent Claims (12, 13)
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14. A receiver comprising:
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an in-phase mixer configured to translate an incoming signal to an in-phase intermediate frequency signal; an in-phase delta-sigma modulator configured to convert the in-phase intermediate frequency signal into an in-phase digital signal at a predetermined sampling rate; an in-phase decimation filter configured to decimate the in-phase digital signal; a quadrature mixer configured to translate the incoming signal to a quadrature intermediate frequency signal; a quadrature delta-sigma modulator configured to convert the quadrature intermediate frequency signal into a quadrature digital signal at the predetermined sampling rate, wherein the quadrature delta-sigma modulator is configured to operate independent of the output of the in-phase delta-sigma modulator and the in-phase delta-sigma modulator is configured to operate independent of the output of the quadrature delta-sigma modulator; a quadrature decimation filter configured to decimate the quadrature digital signal; and a translation circuit configured to translate the decimated in-phase and quadrature digital signals to in-phase and quadrature baseband digital signals; wherein each of the in-phase and quadrature delta-sigma modulators further comprises; an amplifier circuit configured to amplify the respective intermediate signal; wherein the amplifier circuit comprises a first amplifier unit and a second amplifier unit, the output from the first amplifier unit being coupled with the input to the second amplifier unit; and a comparator configured to convert the respective amplified intermediate signal into the respective digital signal at the sampling rate. - View Dependent Claims (15, 16)
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Specification