System and method for memory hub-based expansion bus

• US 7,174,409 B2
• Filed: 04/07/2006
• Issued: 02/06/2007
• Est. Priority Date: 03/25/2004
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Jeddeloh, Joseph M.
• Primary Examiner(s): Ray; Gopal C.
• Application Number:
  US11/399,905
• Publication Number:
  US 20060195647A1
• Time in Patent Office: 305 Days
• Field of Search: 710/100, 710/300, 710/104, 710/311, 710/5, 710/303, 710/2, 710/305, 710/316, 712/11, 712/15, 712/34, 712/220, 365/63, 365/52, 365/230.01, 361/679, 361/684, 345/418, 370/351, 370/338, 370/423, 370/912, 711/105, 711/119, 711/5, 711/149, 713/400, 709/201, 709/219
• US Class Current: 710/311
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/4234 being a memory bus
• CPC Class Codes: G06F 13/4247 on a daisy chain bus
• CPC Class Codes: Y10S 370/912 Packet communications

Abstract

A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupled to the memory hub through a first portion of a memory bus on which the memory requests from the memory hub controller and memory responses from the memory hub are coupled. A second portion of the memory bus couples the memory hub to the processor circuit and is used to couple memory requests from the processor circuit and memory responses provided by the memory hub to the processor circuit.

Claims

1. A method of accessing a system memory having first and second memory modules, each memory module having a plurality of memory devices and a respective memory hub coupled to a respective plurality of memory devices, the memory hubs coupled to each other, the method comprising:

generating memory requests by a memory hub controller for access to the plurality of memory devices of the first memory module;

coupling the memory requests from the memory hub controller to the first memory hub;

generating memory requests by a processor circuit of an expansion module coupled to the second memory hub for access to the plurality of memory devices of the second memory module;

coupling the memory requests from the processor circuit to the second memory hub;

generating memory responses by the second memory hub in response to receiving the memory request from the processor circuit; and

coupling the memory responses from the second memory hub to the processor circuit of the expansion module.

2. The method of claim 1 wherein coupling the memory requests from the processor circuit to the second memory hub comprises coupling the memory requests to a unidirectional upstream bus and coupling the memory responses from the second memory hub to the processor circuit comprises coupling the memory requests to a unidirectional downstream bus.

3. The method of claim 1 wherein generating memory responses by the second memory hub comprises:

coupling the memory request to a memory controller coupled to the plurality of memory devices of the second memory module;

translating the memory request into memory device signals coupled to the plurality of memory devices;

retrieving data from the memory devices in response to the memory device signals; and

generating the memory response including the retrieved data.