Content addressable memory device with source-selecting data translator

• US 7,174,419 B1
• Filed: 05/30/2003
• Issued: 02/06/2007
• Est. Priority Date: 05/30/2003
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Netlogic Microsystems Incorporated (Broadcom, Inc.)
• Inventors: Srinivasan, Varadarajan, Ichiriu, Michael E.
• Primary Examiner(s): Bataille; Pierre
• Assistant Examiner(s): TSAI, SHENG JEN
• Application Number:
  US10/448,819
• Time in Patent Office: 1,348 Days
• Field of Search: 711/108, 365/49
• US Class Current: 711/108
• CPC Class Codes: G11C 15/00 Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
• CPC Class Codes: G11C 15/04 using semiconductor elements

Abstract

A method of operation within a content addressable memory (CAM) device. An input data word having a plurality of data bits and a plurality of mask bits is received in the CAM device. An encoded data word is generated based, at least in part, on states of the mask bits within the input data word. A write data word is selected from a group of data words that includes at least the input data word and the encoded data word. The write data word is stored within a row of CAM cells within the CAM device.

Claims

1. A method of operation within a content addressable memory (CAM) device, the method comprising:

receiving an input data word that includes a plurality of data bits and a plurality of mask bits;

generating an encoded data word based, at least in part, on states of the mask bits;

selecting a write data word from a plurality of data words that includes at least the input data word and the encoded data word, the write data word including the plurality of mask bits and the plurality of data bits if the input data word is selected; and

storing the write data word within a row of CAM cells within the CAM device.

2. The method of claim 1 further comprising receiving an instruction to store the write data word within the CAM device, and wherein selecting the write data word comprises selecting either the input data word or the encoded data word according to the instruction.

3. The method of claim 1 further comprising storing a mode value within the CAM device, and wherein selecting the write data word comprises selecting either the input data word or the encoded data word according to the mode value.

4. The method of claim 1 wherein generating the encoded data word comprises generating a plurality of two-bit data values in which the constituent bits of each two-bit data value are set to a first state if a corresponding one of the mask bits in the input data word is in a mask state, and in which a first constituent bit of each two-bit data value is set to a complement of a corresponding one of the data bits in the input data word if the corresponding one of the mask bits is not in the mask state.

5. The method of claim 1 wherein generating the encoded data value comprises generating the plurality of two-bit data values such that a second constituent bit of each two-bit data value is set to the same state as the corresponding one of the data bits if the corresponding one of the mask bits is in the second state.

6. The method of claim 1 wherein selecting the write data word from a plurality of data words that includes at least the input data word and the encoded data word comprises selecting the write data word from a plurality of data words that additionally includes a read data word obtained from a storage location within the CAM device.

7. The method of claim 1 wherein generating an encoded data word comprises generating an encoded data word that includes the same number of constituent bits as the input data word.

8. A content addressable memory (CAM) device comprising:

an array of CAM cells;

an interface to receive an input data word that includes a plurality of data bits and a plurality of mask bits

an encoding circuit to generate an encoded data word based, at least in part, on states of the mask bits;

a select circuit coupled to receive a plurality of data words, including at least the encoded data word from the encoding circuit and the input data word from the interface, the select circuit being configured to select one of the plurality of data words in response to a select signal; and

a write circuit coupled to the array of CAM cells and coupled to receive the selected one of the plurality of data words from the select circuit, the write circuit being configured to store the selected one of the plurality of data words in the array of CAM cells, wherein the selected one of the plurality of data words includes the plurality of mask bits and the plurality of data bits if the input data word is selected.

9. The CAM device of claim 8 wherein the encoding circuit is configured to generate a plurality of two-bit values in which the constituent bits of each two-bit data value are set to a first state if a corresponding one of the mask bits in the input data word is in a mask state, and in which a first constituent bit of each two-bit data value is set to a complement of a corresponding one of the data bits in the input data word if the corresponding one of the mask bits is not in the mask state.

10. The CAM device of claim 8 wherein the encoding circuit comprises a first plurality of logic gates each coupled to receive a respective one of the data bits as an input data bit and a respective one of the mask bits as an input mask bit, each logic gate of the first plurality of logic gates being configured to output the input data bit if the input mask bit is in a first state, and to output a logic low bit if the input mask bit is in a second state.

11. The CAM device of claim 10 wherein the encoding circuit further comprises a second plurality of logic gates each coupled to receive a respective one of the data bits as an input data bit and a respective one of the mask bits as an input mask bit, each logic gate of the second plurality of logic gates being configured to output a complement of the input data bit if the input mask bit is in the first state and to output a logic low bit if the input mask bit is in a second state.

12. The CAM device of claim 8 wherein the encoding circuit comprises a first plurality of logic circuits each coupled to receive a respective one of the data bits as an input data bit and a respective one of the mask bits as an input mask bit, each logic gate of the first plurality of logic gates being configured to output the input data bit if the input mask bit is in a first state, and to output a logic high bit if the input mask bit is in a second state.

13. The CAM device of claim 8 wherein the select circuit comprises a first input port to receive the input data word, a second input port to receive the encoded data word and a select input to receive the select signal.

14. The CAM device of claim 13 further comprising a read circuit coupled to the CAM array and configured to output a selected data word from the CAM array.

15. The CAM device of claim 14 wherein the select circuit further comprises a third input port coupled to receive the selected data word from the read circuit.

16. The CAM device of claim 8 further comprising a control circuit to receive a write data request, the control circuit being configured to generate the select signal in a state according to the write data request.

17. The CAM device of claim 8 further comprising a configuration circuit to store a write mode value, the configuration circuit being configured to generate the select signal in a state according to the write mode value.

18. The CAM device of claim 8 further comprising an address decoder to enable access to a first subset of the CAM cells in the CAM array in response to a first address value, the write circuit being configured to store the selected one of the plurality of data words within the first subset of the CAM cells in a write operation.

19. The CAM device of claim 18 wherein the address decoder is configured to enable access to a second subset of the CAM cells in the CAM array in response to a second address value, the CAM device further comprising a read circuit coupled to the CAM array and configured to receive an output data word from the second subset of the CAM cells in a read operation.

20. The CAM device of claim 19 wherein the select circuit further comprises a third input port coupled to receive the output data word from the read circuit.

21. A content addressable memory (CAM) device comprising:

an array of CAM cells;

means for generating an encoded data word based, at least in part, on states of mask bits in an input data word that includes a plurality of data bits and a plurality of mask bits;

means for selecting a write data word from a plurality of data words that includes at least the input data word and the encoded data word; and

means for storing the write data word within a row of the CAM cells, wherein the write data word includes the plurality of mask bits and the plurality of data bits if the input data word is selected.

22. The CAM device of claim 21 further comprising means for receiving an instruction to store the write data word within the CAM device, and wherein the means for selecting the write data word comprises means for selecting either the input data word or the encoded data word according to the instruction.

23. The CAM device of claim 21 further comprising storage means for storing a mode value within the CAM device, and wherein the means for selecting the write data word comprises means for selecting either the input data word or the encoded data word according to the mode value.

24. The CAM device of claim 21 wherein the means for generating an encoded data word comprises means for generating an encoded data word that includes the same number of constituent bits as the input data word.