Fabrication of nanoelectronic circuits

• US 7,176,066 B2
• Filed: 05/19/2005
• Issued: 02/13/2007
• Est. Priority Date: 08/31/2000
• Status: Active Grant

• Current Assignee: NewSouth Innovations Pty Limited (University Of New South Wales)
• Original Assignee: Unisearch Limited (University Of New South Wales)
• Inventors: Clark, Robert Graham, Dzurak, Andrew Steven, Hamilton, Alexander Rudolf, Lumpkin, Nancy Ellen, Brenner, Rolf, Buehler, Tilo Marcus, McKinnon, Rita Paytricia
• Primary Examiner(s): Mulpuri; Savitri
• Application Number:
  US11/132,851
• Publication Number:
  US 20050214689A1
• Time in Patent Office: 635 Days
• Field of Search: 438/584, 438/587, 438/622, 438/637, 438/2, 438/20, 438/510, 438/525, 438/142, 257/E21.404
• US Class Current: 438/142
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G06N 10/00 Quantum computing, i.e. information processing based on quantum-mechanical phenomena
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H10N 99/05 Devices based on quantum mechanical effects, e.g. quantum interference devices or metal single-electron transistors

Abstract

A silicon substrate is coated with one or more layers of resist. First and second circuit patterns are exposed in sequence, where the second pattern crosses the first pattern. The patterned resist layers are developed to open holes which extend down to the substrate only where the patterns cross over each other. These holes provide a mask suitable for implanting single phosphorous ions in the substrate, for a solid state quantum computer. Further development of the resist layers provides a mask for the deposition of nanoelectronic circuits, such as single electron transistors, aligned to the phosphorous ions.

Claims

1. A method for fabricating nanoelectric circuits, including the steps of:

coating a semiconductor substrate surface with one or more layers of resist;

exposing a first circuit pattern into the one or more layers of resist;

exposing a second circuit pattern into the one or more layers of resist, after the first circuit pattern has been exposed into the one or more layers of resist, such that the second circuit pattern crosses the previously exposed pattern;

developing the one or more layers of resist to open holes through the one or more layers of resist only where the patterns cross each other; and

implanting an ion through each hole;

the method including the further step of evaporating metal at different angles through the one or more layers of resist remaining to create active devices and conducting control gates on the semiconductor substrate surface positioned relative to the implanted ions as determined by the angle of evaporation.

18. A method according to claim 1, comprising the additional step of:

evaporating metal at a first angle through the resist layers.

21. A method according to claim 1, where part of the circuit pattern for the active devices and conducting control gates is a series of parallel straight lines and the other pattern is a straight line transverse to the straight lines of the circuit pattern for the active devices and conducting control gates.

2. A method for fabricating nanoelectric circuits, including the steps of:

coating a semiconductor substrate surface with one or more layers of resist;

exposing a first circuit pattern into the one or more layers of resist;

exposing a second circuit pattern into the one or more layers of resist, after the first circuit pattern has been exposed into the one or more layers of resist, such that the second circuit pattern crosses the previously exposed pattern;

developing the one or more layers of resist to open holes through the one or more layers of resist only where the patterns cross each other; and

implanting an ion through each hole;

where one circuit pattern defines the geometry of active devices and conducting control gates, and another circuit pattern defines the locus on which the holes are to be opened for the ion implantation.

19. A method according to claim 2, comprising the additional step of:

oxidising the surface of the deposited metal.

22. A method according to claim 2, where part of the circuit pattern for the active devices and conducting control gates is a series of parallel straight lines and the other pattern is a straight line transverse to the straight lines of the circuit pattern for the active devices and conducting control gates.

3. A method for fabricating nanoelectric circuits, including the steps of:

coating a semiconductor substrate surface with one or more layers of resist;

exposing a first circuit pattern into the one or more layers of resist;

exposing a second circuit pattern into the one or more layers of resist, after the first circuit pattern has been exposed into the one or more layers of resist, such that the second circuit pattern crosses the previously exposed pattern;

developing the one or more layers of resist to open holes through the one or more layers of resist only where the patterns cross each other; and

implanting an ion through each hole;

where both circuit patterns are written with the same resolution and accuracy as each other.

20. A method according to claim 3, comprising the additional step of:

evaporating metal at a second angle through the resist layers.

23. A method according to claim 3, where part of the circuit pattern for the active devices and conducting control gates is a series of parallel straight lines and the other pattern is a straight line transverse to the straight lines of the circuit pattern for the active devices and conducting control gates.

4. A method for fabricating nanoelectric circuits, including the steps of:

coating a semiconductor substrate surface with one or more layers of resist;

exposing a first circuit pattern into the one or more layers of resist;

exposing a second circuit pattern into the one or more layers of resist, after the first circuit pattern has been exposed into the one or more layers of resist, such that the second circuit pattern crosses the previously exposed pattern;

developing the one or more layers of resist to open holes through the one or more layers of resist only where the patterns cross each other; and

implanting an ion through each hole;

the method utilizing a multi-layer resist through which one or more ions are implanted through each hole, and a multi-angle metal deposition being used to create the active devices and the control gates registered above the implanted ions, wherein the circuits are suitable for solid state quantum computer control and read-out.

5. A method for fabricating nanoelectric circuits, including the steps of:

coating a semiconductor substrate surface with one or more layers of resist;

exposing a first circuit pattern into the one or more layers of resist;

exposing a second circuit pattern into the one or more layers of resist, after the first circuit pattern has been exposed into the one or more layers of resist, such that the second circuit pattern crosses the previously exposed pattern;

developing the one or more layers of resist to open holes through the one or more layers of resist only where the patterns cross each other; and

implanting an ion through each hole;

in which method a three-layer resist is used, and a double-angle or triple-angle metal deposition is used, wherein the circuits are suitable for solid state quantum computer control and read-out.

6. A method for fabricating nanoelectric circuits, comprising the steps of:

coating a semiconductor substrate with a layer of a first resist;

writing a first pattern for the locus of ion positions into the first resist;

developing the first resist into which has been written the first pattern;

coating the semiconductor substrate, over the first resist which has been developed, with a layer of a second resist and then with a layer of a third resist of sensitivity lower than sensitivity of the second resist where both the second and third resists use a different developer process compared to the developer process used for the first resist;

writing a second pattern for metal circuitry into the resist layers such that the second pattern crosses over the first pattern;

partially developing the resist layers, into which has been written the second pattern, such that trenches are opened in the second and third resists only where the second pattern is defined, and such that holes down to the silicon substrate are opened only where the first and second patterns cross each other; and

implanting one or more ions through each hole;

the method utilizing a multi-layer resist through which one or more ions are implanted through each hole, and a multi-angle metal deposition being used to create the active devices and the control gates registered above the implanted ions.

7. A method according to claim 6, comprising the additional step of:

implanting single ions through each hole.

8. A method according to claim 7, comprising the additional step of:

fully developing the resist layers, into which has been written the second pattern, to create a cavity region under the third resist.

9. A method according to claim 8, comprising the additional step of:

removing the remainder of the first resist which lies within the cavity region.

10. A method according to claim 9, comprising the additional step of:

evaporating metal at a first angle through the resist layers.

11. A method according to claim 10, comprising the additional step of:

oxidising the surface of the deposited metal.

12. A method according to claim 11, comprising the additional step of:

evaporating metal at a second angle through the resist layers.

13. A method according to claim 12, comprising the additional step of:

evaporating metal at a third angle through the resist layers.

14. A method according to claim 13, comprising the additional step of:

lifting-off all resist layers in solvents to reveal a completed device.

15. A method according to claim 14, comprising the additional step of:

passivating or glassivating the surface as required.

16. A method according to claim 15, comprising the additional step of:

annealing the device to activate dopants and remove ion-beam damage.

17. A method for fabricating nanoelectric circuits comprising the steps of:

coating a semiconductor substrate with a layer of a first resist;

writing a first pattern for the locus of ion positions into the first resist;

developing the first resist into which has been written the first pattern;

coating the semiconductor substrate, over the first resist which has been developed, with a layer of a second resist and then with a layer of a third resist of sensitivity lower than sensitivity of the second resist, where both the second and third resists use a different developer process compared to the developer process used for the first resist;

writing a second pattern for metal circuitry into the resist layers such that the second pattern crosses over the first pattern;

partially developing the resist layers, into which has been written the second pattern, such that trenches are opened in the second and third resist only where the second pattern is defined, and such that holes down to the silicon substrate are opened only where the first and second patterns cross each other; and

implanting one or more ions through each hole;

the method of utilizing a multi-layer resist through which one or more ions are implanted through each hole, and a multi-angle metal deposition being used to create the active devices and the control gates registered above the implanted ions.