Fabrication of nanoelectronic circuits
First Claim
Patent Images
1. A method for fabricating nanoelectric circuits, including the steps of:
- coating a semiconductor substrate surface with one or more layers of resist;
exposing a first circuit pattern into the one or more layers of resist;
exposing a second circuit pattern into the one or more layers of resist, after the first circuit pattern has been exposed into the one or more layers of resist, such that the second circuit pattern crosses the previously exposed pattern;
developing the one or more layers of resist to open holes through the one or more layers of resist only where the patterns cross each other; and
implanting an ion through each hole;
the method including the further step of evaporating metal at different angles through the one or more layers of resist remaining to create active devices and conducting control gates on the semiconductor substrate surface positioned relative to the implanted ions as determined by the angle of evaporation.
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Abstract
A silicon substrate is coated with one or more layers of resist. First and second circuit patterns are exposed in sequence, where the second pattern crosses the first pattern. The patterned resist layers are developed to open holes which extend down to the substrate only where the patterns cross over each other. These holes provide a mask suitable for implanting single phosphorous ions in the substrate, for a solid state quantum computer. Further development of the resist layers provides a mask for the deposition of nanoelectronic circuits, such as single electron transistors, aligned to the phosphorous ions.
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Citations
23 Claims
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1. A method for fabricating nanoelectric circuits, including the steps of:
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coating a semiconductor substrate surface with one or more layers of resist; exposing a first circuit pattern into the one or more layers of resist; exposing a second circuit pattern into the one or more layers of resist, after the first circuit pattern has been exposed into the one or more layers of resist, such that the second circuit pattern crosses the previously exposed pattern; developing the one or more layers of resist to open holes through the one or more layers of resist only where the patterns cross each other; and implanting an ion through each hole; the method including the further step of evaporating metal at different angles through the one or more layers of resist remaining to create active devices and conducting control gates on the semiconductor substrate surface positioned relative to the implanted ions as determined by the angle of evaporation. - View Dependent Claims (18, 21)
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2. A method for fabricating nanoelectric circuits, including the steps of:
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coating a semiconductor substrate surface with one or more layers of resist; exposing a first circuit pattern into the one or more layers of resist; exposing a second circuit pattern into the one or more layers of resist, after the first circuit pattern has been exposed into the one or more layers of resist, such that the second circuit pattern crosses the previously exposed pattern; developing the one or more layers of resist to open holes through the one or more layers of resist only where the patterns cross each other; and implanting an ion through each hole; where one circuit pattern defines the geometry of active devices and conducting control gates, and another circuit pattern defines the locus on which the holes are to be opened for the ion implantation. - View Dependent Claims (19, 22)
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3. A method for fabricating nanoelectric circuits, including the steps of:
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coating a semiconductor substrate surface with one or more layers of resist; exposing a first circuit pattern into the one or more layers of resist; exposing a second circuit pattern into the one or more layers of resist, after the first circuit pattern has been exposed into the one or more layers of resist, such that the second circuit pattern crosses the previously exposed pattern; developing the one or more layers of resist to open holes through the one or more layers of resist only where the patterns cross each other; and implanting an ion through each hole; where both circuit patterns are written with the same resolution and accuracy as each other. - View Dependent Claims (20, 23)
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4. A method for fabricating nanoelectric circuits, including the steps of:
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coating a semiconductor substrate surface with one or more layers of resist; exposing a first circuit pattern into the one or more layers of resist; exposing a second circuit pattern into the one or more layers of resist, after the first circuit pattern has been exposed into the one or more layers of resist, such that the second circuit pattern crosses the previously exposed pattern; developing the one or more layers of resist to open holes through the one or more layers of resist only where the patterns cross each other; and implanting an ion through each hole; the method utilizing a multi-layer resist through which one or more ions are implanted through each hole, and a multi-angle metal deposition being used to create the active devices and the control gates registered above the implanted ions, wherein the circuits are suitable for solid state quantum computer control and read-out.
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5. A method for fabricating nanoelectric circuits, including the steps of:
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coating a semiconductor substrate surface with one or more layers of resist; exposing a first circuit pattern into the one or more layers of resist; exposing a second circuit pattern into the one or more layers of resist, after the first circuit pattern has been exposed into the one or more layers of resist, such that the second circuit pattern crosses the previously exposed pattern; developing the one or more layers of resist to open holes through the one or more layers of resist only where the patterns cross each other; and implanting an ion through each hole; in which method a three-layer resist is used, and a double-angle or triple-angle metal deposition is used, wherein the circuits are suitable for solid state quantum computer control and read-out.
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6. A method for fabricating nanoelectric circuits, comprising the steps of:
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coating a semiconductor substrate with a layer of a first resist; writing a first pattern for the locus of ion positions into the first resist; developing the first resist into which has been written the first pattern; coating the semiconductor substrate, over the first resist which has been developed, with a layer of a second resist and then with a layer of a third resist of sensitivity lower than sensitivity of the second resist where both the second and third resists use a different developer process compared to the developer process used for the first resist; writing a second pattern for metal circuitry into the resist layers such that the second pattern crosses over the first pattern; partially developing the resist layers, into which has been written the second pattern, such that trenches are opened in the second and third resists only where the second pattern is defined, and such that holes down to the silicon substrate are opened only where the first and second patterns cross each other; and implanting one or more ions through each hole; the method utilizing a multi-layer resist through which one or more ions are implanted through each hole, and a multi-angle metal deposition being used to create the active devices and the control gates registered above the implanted ions. - View Dependent Claims (7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A method for fabricating nanoelectric circuits comprising the steps of:
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coating a semiconductor substrate with a layer of a first resist; writing a first pattern for the locus of ion positions into the first resist; developing the first resist into which has been written the first pattern; coating the semiconductor substrate, over the first resist which has been developed, with a layer of a second resist and then with a layer of a third resist of sensitivity lower than sensitivity of the second resist, where both the second and third resists use a different developer process compared to the developer process used for the first resist; writing a second pattern for metal circuitry into the resist layers such that the second pattern crosses over the first pattern; partially developing the resist layers, into which has been written the second pattern, such that trenches are opened in the second and third resist only where the second pattern is defined, and such that holes down to the silicon substrate are opened only where the first and second patterns cross each other; and implanting one or more ions through each hole; the method of utilizing a multi-layer resist through which one or more ions are implanted through each hole, and a multi-angle metal deposition being used to create the active devices and the control gates registered above the implanted ions.
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Specification