Method for making a semiconductor device that includes a metal gate electrode

• US 7,176,090 B2
• Filed: 09/07/2004
• Issued: 02/13/2007
• Est. Priority Date: 09/07/2004
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Shah, Uday, Chau, Robert S., Doczy, Mark L., Kavalieros, Jack, Doyle, Brian S., Brask, Justin K., Metz, Matthew V., Datta, Suman
• Primary Examiner(s): Estrada; Michelle
• Application Number:
  US10/936,114
• Publication Number:
  US 20060051957A1
• Time in Patent Office: 889 Days
• Field of Search: 438/199, 438/270, 438/275, 438/585, 438/638, 438/926, 438/FOR.187, 438/FOR.216, 438/FOR.238, 438/201, 438/294, 438/588, 257/E27.06, 257/E27.108, 257/E29.126
• US Class Current: 438/270
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/30608 Anisotropic liquid etching H01L21/3063 takes precedence
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: Y10S 438/926 Dummy metallization

Abstract

A method for making a semiconductor device is described. That method comprises forming on a substrate a dielectric layer and a sacrificial structure that comprises a first layer and a second layer, such that the second layer is formed on the first layer and is wider than the first layer. After the sacrificial structure is removed to generate a trench, a metal gate electrode is formed within the trench.

Claims

1. A method for making a semiconductor device comprising:

forming a first dielectric layer on a substrate;

forming on the first dielectric layer a sacrificial structure that comprises a first layer and a second layer, the second layer being formed on the first layer and the second layer being wider than the first layer;

forming a second dielectric layer on the first dielectric layer, wherein the second dielectric layer encases the sacrificial structure;

planarizing the second dielectric layer to expose a top surface of the sacrificial layer;

removing the sacrificial structure to generate a trench having sidewalls and a bottom that is nested within the second dielectric layer;

forming a conformal high-k gate dielectric layer on the sidewalls and bottom of the trench; and

then

forming a tapered metal gate electrode on the high-k gate dielectric layer within the trench, wherein the tapered metal gate electrode comprises a first metal layer and a second metal layer, the second metal layer being formed on the first metal layer and the second metal layer being wider than the first metal layer.

2. The method of claim 1 further comprising:

removing a portion of the first dielectric layer after removing the sacrificial structure.

3. The method of claim 1 wherein the first layer comprises germanium and the second layer comprises silicon.

4. The method of claim 3 wherein the sacrificial structure is formed by forming a silicon containing layer on a germanium containing layer, then exposing the silicon containing layer and the germanium containing layer to an aqueous solution that comprises hydrogen peroxide.

5. The method of claim 1 wherein the first layer comprises silicon and the second layer comprises germanium.

6. The method of claim 5 wherein the sacrificial structure is formed by forming a germanium containing layer on a silicon containing layer, then exposing the germanium containing layer and the silicon containing layer to an aqueous solution that comprises a source of hydroxide.

7. The method of claim 6 wherein the source of hydroxide comprises ammonium hydroxide or tetramethyl ammonium hydroxide.

8. The method of claim 1 wherein the first dielectric layer is a high-k gate dielectric layer.

14. The method of claim 1, wherein the first layer has a width that is at least about 100 angstroms smaller than the width of the second layer.

19. The method of claim 1 wherein the high-k gate dielectric layer is less than about 40 angstroms thick, and comprises a material that is selected from the group consisting of hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

20. The method of claim 1 wherein the tapered metal gate electrode comprises a metal that is selected from the group consisting of hafnium, zirconium, titanium, tantalum, aluminum, a metal carbide, an aluminide, ruthenium, palladium, platinum, cobalt, nickel, and a conductive metal oxide.

9. A method for making a semiconductor device comprising:

forming a first dielectric layer on a substrate;

forming a first layer on the first dielectric layer;

forming a second layer on the first layer;

forming a sacrificial structure using an aqueous solution to remove portions of the first dielectric layer, the first layer, and the second layer, wherein the aqueous solution removes substantially more of the first layer and the first dielectric layer than the second layer;

forming a second dielectric layer on the substrate;

removing the sacrificial structure to generate a trench within the second dielectric layer;

forming a conformal high-k gate dielectric layer on the substrate and within the trench; and

then

forming a tapered metal gate electrode within the trench and on the high-k gate dielectric layer, wherein the tapered metal gate electrode comprises a first metal layer and a second metal layer, the second metal layer being formed on the first metal layer and the second metal layer being wider than the first metal layer.

10. The method of claim 9 wherein the first layer comprises germanium and is between about 100 angstroms and about 500 angstroms thick, and the second layer comprises silicon and is between about 400 angstroms and about 800 angstroms thick.

11. The method of claim 10 wherein the first layer and the second layer are exposed to an aqueous solution that comprises between about 2 percent and about 5 percent of hydrogen peroxide by volume.

12. The method of claim 9 wherein the first layer comprises silicon and is between about 100 angstroms and about 500 angstroms thick, and the second layer comprises germanium and is between about 400 angstroms and about 800 angstroms thick.

13. The method of claim 12 wherein the first layer and the second layer are exposed to an aqueous solution that comprises between about 2 percent and about 15 percent of ammonium hydroxide or tetramethyl ammonium hydroxide by volume.

15. The method of claim 9 wherein:

the first layer comprises germanium and is between about 100 angstroms and about 500 angstroms thick;

the second layer comprises silicon and is between about 400 angstroms and about 800 angstroms thick; and

the first layer has a width that is less than about 300 angstroms after portions of the first layer are removed.

16. The method of claim 15 wherein the aqueous solution comprises between about 2 percent and about 5 percent of hydrogen peroxide by volume.

17. The method of claim 9 wherein:

the first layer comprises silicon and is between about 100 angstroms and about 500 angstroms thick;

the second layer comprises germanium and is between about 400 angstroms and about 800 angstroms thick; and

the first layer has a width that is less than about 300 angstroms after portions of the first sacrificial layer are removed.

18. The method of claim 17 wherein the aqueous solution comprises between about 2 percent and about 15 percent of ammonium hydroxide or tetramethyl ammonium hydroxide by volume.