Methods of fabricating highly conductive regions in semiconductor substrates for radio frequency applications

• US 7,176,129 B2
• Filed: 11/19/2002
• Issued: 02/13/2007
• Est. Priority Date: 11/20/2001
• Status: Active Grant

• Current Assignee: 2001-241-2, Regents of the University of California (University of California)
• Original Assignee: Regents of the University of California (University of California)
• Inventors: Xie, Ya-Hong, Yeh, Chang-Ching, Tu, King-Ning
• Primary Examiner(s): Lebentritt; Michael
• Assistant Examiner(s): STEVENSON, ANDRE C
• Application Number:
  US10/299,451
• Publication Number:
  US 20030148598A1
• Time in Patent Office: 1,547 Days
• Field of Search: 438/381, 438/400, 438/405, 438/430, 438453-454, 438/466, 438/469, 438597-598, 438/674, 438/762, 438765-766, 438769-772, 438/960
• US Class Current: 438/667
• CPC Class Codes: H01L 21/76 Making of isolation regions between components
• CPC Class Codes: H01L 21/76227 the dielectric materials being obtained by full chemical transformation of non-dielectric materials, such as polycristalline silicon, metals
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

Methods of fabricating highly conductive regions in semiconductor substrates for radio frequency applications are used to fabricate two structures: (1) a first structure includes porous Si (silicon) regions extending throughout the thickness of an Si substrate that allows for the subsequent formation of metallized posts and metallized moats in the porous regions; and (2) a second structure includes staggered deep V-grooves or trenches etched into an Si substrate, or some other semiconductor substrate, from the front and/or the back of the substrate, wherein these V-grooves and trenches are filled or coated with metal to form the metallized moats.

Claims

1. A method of fabricating highly conductive regions in semiconductor substrates for radio frequency applications, comprising:

forming one or more porous Si (silicon) regions on a Si substrate by anodization; and

isolating a noisy circuit area on the Si substrate from a noise sensitive circuit area on the Si substrate by depositing one or more metals into the porous Si regions to create a metallized, localized porous Si region comprising a moat or trench that extends through the Si substrate and laterally separates the noisy circuit area from the noise sensitive circuit area on the surface of the Si substrate.

2. The method of claim 1, wherein the forming step comprises:

exposing a surface of the Si substrate to HF (hydrogen fluoride) containing an electrolyte; and

passing an electrical current through a Si-electrolyte interface with the Si substrate acting as the anode in order to form the porous Si regions on the Si substrate.

3. The method of claim 2, further comprising adjusting the HF concentration in the electrolyte and the electrical current density during anodization to alter a microstructure of the porous Si regions.

4. The method of claim 1, wherein the metals are deposited into the porous Si regions by vapor deposition, solid state interdiffusion and reaction, or liquid state penetration.

5. The method of claim 1, wherein the metal is Au (gold) or Al (aluminum).

6. The method of claim 5, wherein a penetration by Au is followed with a penetration by molten Sn (tin) or an Sn-based solder.

7. The method of claim 1, further comprising creating one or more metallized posts, in the noisy circuit area, from the metallized, localized porous Si regions, wherein the metallized posts extend through the substrate and act as true ground points.