Semiconductor integrated circuit

• US 7,176,487 B2
• Filed: 04/14/2005
• Issued: 02/13/2007
• Est. Priority Date: 04/16/2004
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Kikuchi, Takafumi, Sakamoto, Noriaki, Ito, Fujio, Sato, Tomoru, Yokohama, Takehisa
• Primary Examiner(s): CLARK, JASMINE JHIHAN B
• Application Number:
  US11/105,482
• Publication Number:
  US 20050230796A1
• Time in Patent Office: 670 Days
• Field of Search: 257/48, 257/522, 257/666, 257/691, 257/678, 257/723, 257/777, 257/735, 257/736, 257/E23.014, 257/E23.079, 438 11- 18, 438611-618, 324/765
• US Class Current: 257/48
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/29007 Layer connector smaller than the underlying bonding area
• CPC Class Codes: H01L 2224/32014 the layer connector being smaller than the bonding area, e.g. bond pad
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4943 the connecting portions being staggered
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/92247 the second connecting process involving a wire connector
• CPC Class Codes: H01L 2225/06596 Structural arrangements for testing
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01038 : Strontium [Sr]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01055 : Cesium [Cs]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/10161 : with a rectangular active surface
• CPC Class Codes: H01L 2924/10162 : with a square active surface
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3512 : Cracking

Abstract

To provide a test technology capable of reducing a package size by reducing a number of terminals (pins) in a semiconductor integrated circuit of SIP or the like constituted by mounting a plurality of semiconductor chips to a single package, in SIP 102 constituted by mounting a plurality of semiconductor chips to a signal package of ASIC 100, SDRAM 101 and the like, a circuit of testing SDRAM 101 (SDRAMBIST 109) is provided at inside of ASIC 100, and SDRAM 101 is tested from outside of SDRAM 101, that is, from ASIC 100. By providing the test circuit of SDRAM 101 at inside of ASIC 100, it is not necessary to extrude a terminal for testing SDRAM 101 to outside of SIP 102.

Claims

1. A semiconductor device which includes a first semiconductor chip and a second semiconductor chip on a signal package,

the first semiconductor chip being a system chip and including a test circuit for testing the second semiconductor chip, and

the second semiconductor chip being a memory chip,

the first semiconductor chip including:

an input/output buffer having a control signal input and

a first terminal coupled to the input/output buffer,

the second semiconductor chip including;

a second terminal coupled to the first terminal only at inside of the single package and not coupled to an external terminal of the single package, and

the input/output buffer having a function of charging or discharging the first terminal and the second terminal by making a control signal ON, bringing the first terminal and the second terminal into a high impedance state by making the control signal OFF and detecting voltage levels of the first terminal and the second terminal after elapse of a predetermined time period.

2. A semiconductor device which includes a first semiconductor chip and a second semiconductor chip on a signal package,

the first semiconductor chip including:

an input/output buffer having a control signal input and

a first terminal coupled to the input/output buffer,

the second semiconductor chip including;

a second terminal coupled to the first terminal only at inside of the single package and not coupled to an external terminal of the single package, and

the input/output buffer having a function of charging or discharging the first terminal and the second terminal by making a control signal ON, bringing the first terminal and the second terminal into a high impedance state by making the control signal OFF and detecting voltage levels of the first terminal and the second terminal after elapse of a predetermined time period.

3. The semiconductor device according to claim 2, wherein the first semiconductor chip further includes:

a third terminal for outputting a detecting signal of the voltage levels of the first terminal and the second terminal detected by the input/output buffer, and

wherein the third terminal is coupled to the external terminal of the single package.

4. The semiconductor device according to claim 2,

wherein the first semiconductor chip further includes means for maintaining the detecting signal of the voltage levels of the first terminal and the second terminal detected by the input/output buffer.

5. The semiconductor device according to claim 2,

wherein the first semiconductor chip is a system chip, and

wherein the second semiconductor chip is a memory chip.

6. The semiconductor device which includes a first semiconductor chip and a second semiconductor chip on a signal package,

the first semiconductor chip being a system chip and including a test circuit for testing the second semiconductor chip, and

the second semiconductor chip being a memory chip,

wherein the first semiconductor chip includes a semiconductor element and a plurality of electrodes at a main face thereof,

wherein the second semiconductor chip includes a semiconductor element and a plurality of electrodes at a main face thereof and is arranged to align laterally with the first semiconductor chip,

wherein a thickness of the second semiconductor chip is thinner than that of the first semiconductor chip, and

wherein the semiconductor device further including:

a first chip mounting portion coupled to the first semiconductor chip;

a second chip mounting portion coupled to the semiconductor chip;

a plurality of leads arranged at surroundings of the first semiconductor chip and the second semiconductor chip;

a plurality of conductive first bonding wires for respectively electrically coupling the electrode of the first semiconductor chip and the electrode of the second semiconductor chip;

a plurality of conductive second bonding wires for respectively electrically coupling the electrode of the first semiconductor chip and the lead, arranged to ride over the second semiconductor chip and formed with a loop at a position higher than a loop of the first bonding wire; and

a seal member for sealing the first semiconductor chip, the second semiconductor chip, the plurality of first bonding wires and the plurality of second bonding wires by a resin.