Thin film transistor for liquid crystal display and method of manufacturing the same

• US 7,176,494 B2
• Filed: 06/25/2004
• Issued: 02/13/2007
• Est. Priority Date: 05/14/2001
• Status: Expired due to Term

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Dong-Gyu
• Primary Examiner(s): Soward; Ida M.
• Application Number:
  US10/876,007
• Publication Number:
  US 20040227864A1
• Time in Patent Office: 963 Days
• Field of Search: 257/57, 257/59, 257/66, 257 72- 73, 257/291
• US Class Current: 257/72
• CPC Class Codes: G02F 1/13458 Terminal pads
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/136231 for reducing the number of lithographic steps
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1244 for preventing breakage, peeling or short circuiting
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/78669 with inverted-type structure, e.g. with bottom gate
• CPC Class Codes: Y10S 438/942 Masking
• CPC Class Codes: Y10S 438/945 Special, e.g. metal
• CPC Class Codes: Y10S 438/948 Radiation resist
• CPC Class Codes: Y10S 438/949 Energy beam treating radiation resist on semiconductor

Abstract

Disclosed is a thin film transistor (TFT) for a liquid crystal display (LCD) and a method for manufacturing the same that allows the number of photomasks used in a photolithography process to be decreased as compared to conventional methods. A passivation film is formed as a single layered organic insulating film, and the number of needed exposure steps is reduced, so as to decrease the number of needed photomask sheets and thereby improve the efficiency of the TFT production process. Applications of the disclosed method include reflection and transmission composite type LCDs as well as a reflection type LCD.

Claims

1. A thin film transistor for a liquid crystal display (LCD), comprising:

a gate wiring formed on a substrate including a display region and a pad region positioned at an outer portion of the display region, said gate wiring extending in a first direction;

a gate insulating film formed on the gate wiring and the substrate, for partially exposing the gate wiring;

an active pattern formed on the gate insulating film;

a data wiring partially overlapped with the active pattern, the data wiring formed on the gate insulating film and extending in a second direction substantially perpendicular to the first direction;

an organic passivation film pattern formed on the data wiring and the gate insulating film, said organic passivation film pattern including a first via hole to partially expose the data wiring and a second via hole to partially expose the gate wiring;

a pixel electrode formed on the organic passivation film pattern and connected to the data wiring through the first via hole; and

,

a pad electrode formed on the organic passivation film pattern and connected to the gate wiring through the second via hole,

wherein the data wiring comprises a stepped portion arranged on a surface of the data wiring in the first via hole.

2. The thin film transistor of claim 1, wherein the gate insulating film extends from a sidewall of the second via hole.

3. The thin film transistor of claim 1, wherein the gate wiring comprises a gate line including a gate electrode formed within the display region and a gate pad formed at the pad region, the gate pad is connected to an end of the gate line and the second via hole is formed on the gate pad.

4. The thin film transistor of claim 1, wherein the data wiring comprises a first electrode overlapped with a first region of the active pattern and a second electrode overlapped with a second region of the active pattern, the second region arranged opposite to the first region, and the first via hole is formed on the first electrode.

5. The thin film transistor of claim 1, further comprising a data pad arranged at the pad region and formed from the same layer as the gate wiring.

6. The thin film transistor of claim 5, further comprising a bridge electrode formed on the organic passivation film pattern, the bridge electrode is from the same layer as the pixel electrode and the bridge electrode connects an end of the data wiring with the data pad through a third via hole formed in the organic passivation film pattern on the end of the data wiring and a fourth via hole formed at both the gate insulating film and the organic passivation film pattern on the data pad.

7. The thin film transistor of claim 1, wherein the organic passivation film pattern has an irregular upper surface at the display region.

8. The thin film transistor of claim 1, wherein the pixel electrode further comprises a double layered structure including a transparent electrode and a reflection electrode.

9. The thin film transistor of claim 8, wherein the pad electrode comprises a single layer of the transparent electrode.