Memory cell and method for forming the same

• US 7,176,513 B2
• Filed: 11/09/2004
• Issued: 02/13/2007
• Est. Priority Date: 06/21/2002
• Status: Expired due to Term

• Current Assignee: Nanya Technology Corporation
• Original Assignee: Micron Technology, Inc.
• Inventors: Brown, Kris K.
• Primary Examiner(s): Dang; Phuc T.
• Application Number:
  US10/985,182
• Publication Number:
  US 20050082588A1
• Time in Patent Office: 826 Days
• Field of Search: 257/300, 257/302, 257/327, 257/329, 257/330, 257/333, 257/378, 257/389
• US Class Current: 257/300
• CPC Class Codes: H01L 28/90 having vertical extensions
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/31 having a storage electrode stacked over the transistor

Abstract

A semiconductor memory cell structure and method for forming the same. The memory cell is formed on a surface of a substrate and includes an active region formed in the substrate, an epitaxial post formed on the surface of the substrate over the active region. The epitaxial post has at least one surface extending outwardly from the surface of the substrate and another surface opposite of the surface of the substrate. A gate structure is formed adjacent to at least a portion of all the outwardly extending surfaces of the epitaxial post, and a capacitor formed on an exposed surface of the epitaxial post.

Claims

1. A memory device having an address bus and a data terminal, comprising:

an array of memory cells formed on a substrate including silicon, the memory cells arranged in rows and columns, each of the rows having a word line and each of the columns having a bit line;

a row address circuit coupled to the address bus for activating the word line in the array corresponding to a row address applied to the row address circuit through the address bus;

a column address circuit coupled to the address bus for coupling an I/O line for the array to the bit line corresponding to a column address applied to the column address circuit through the address bus; and

a sense amplifier having an input coupled to a data line and an output coupled to the data terminal of the memory device, wherein each memory cell comprises;

an active region formed in a substrate;

an epitaxial post formed over the active region, the epitaxial post defined by at least one surface facing away from a surface of the substrate and at least two peripheral surfaces;

a transfer gate formed adjacent to the at least two peripheral surfaces of the epitaxial post; and

a memory cell capacitor formed over the at least one surface facing away from the surface of the substrate.

2. The memory device of claim 1, wherein the memory cells further comprise an insulating layer formed over the at least two peripheral surfaces.

3. The memory device of claim 1, wherein the transfer gate of the memory cells comprises:

a gate oxide formed on the at least one peripheral surface of the epitaxial post; and

a polysilicon gate formed on the gate oxide.

4. The memory device of claim 1, wherein the of the memory cells further comprise:

a insulating layer formed over the active region;

an opening through the insulating layer to expose a portion of the active region; and

a conductive material formed in the opening and on the active region to be electrically coupled thereto.

5. The memory device of claim 1, wherein the of the memory cells further comprise an insulating material formed over the transfer gate to electrically insulate the transfer gate.

6. The memory device of claim 1, wherein the active region of the memory cells comprises a buried digit line.

7. The memory device of claim 1, wherein the memory cell capacitor of the memory cells comprises a container shaped capacitor structure.

8. The memory device of claim 1, wherein the epitaxial post of the memory cells comprises an epitaxial post having a polygonal cross-sectional area.

9. The memory device of claim 1, wherein the transfer gate extends peripherally about the epitaxial post.

10. The memory device of claim 1, wherein the epitaxial post comprises a channel region.

11. A memory device having an address bus and a data terminal, comprising:

an array of memory cells formed on a substrate including silicon, the memory cells arranged in rows and columns, each of the rows having a word line and each of the columns having a bit line;

a row address circuit coupled to the address bus for activating the word line in the array corresponding to a row address applied to the row address circuit through the address bus;

a column address circuit coupled to the address bus for coupling an I/O line for the array to the bit line corresponding to a column address applied to the column address circuit through the address bus; and

a sense amplifier having an input coupled to a data line and an output coupled to the data terminal of the memory device, wherein each memory cell comprises;

an active region formed in a substrate having a surface;

a vertical transistor at least partially formed in an epitaxial post, the epitaxial post formed on the surface of the substrate and extending therefrom, the vertical transistor further having a gate formed around a perimeter of the epitaxial post; and

a capacitor formed on the vertical transistor.

12. The memory device of claim 11, wherein the vertical transistor of each memory cell comprises:

a gate oxide formed on a surface defining the perimeter of the epitaxial post, the gate being formed on the gate oxide; and

insulating sidewalls formed on the gate.

13. The memory device of claim 11, wherein the gate of each memory cell comprises polysilicon.

14. The memory device of claim 11, wherein the capacitor of each memory cell comprises a container shaped capacitor structure.

15. The memory device of claim 11, wherein each memory cell further comprises a diffusion region in the epitaxial post adjacent the capacitor.

16. The memory device of claim 11, wherein the active region of each memory cell comprises a buried digit line.

17. The memory device of claim 11, wherein each memory cell further comprises a digit line contact formed over the active region and proximate the vertical transistor.

18. The memory device of claim 11, wherein each memory cell further comprises an insulating region formed around the perimeter of the epitaxial post and interposed between the capacitor and the vertical transistor.

19. The memory device of claim 11, wherein the epitaxial post each memory cell comprises a channel region.