Semiconductor device and method of fabricating same

• US 7,176,527 B2
• Filed: 10/10/2003
• Issued: 02/13/2007
• Est. Priority Date: 04/10/2003
• Status: Expired due to Fees

• Current Assignee: Oki Semiconductor Company Limited (ROHM Co., Ltd.)
• Original Assignee: OKI Electric Industry Company Limited
• Inventors: Fukuda, Koichi
• Primary Examiner(s): Soward; Ida M.
• Application Number:
  US10/682,477
• Publication Number:
  US 20040201063A1
• Time in Patent Office: 1,222 Days
• Field of Search: 257347-354, 257/336, 257/344, 257372-373, 257/386, 257/394, 257/408
• US Class Current: 257/347
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/78612 for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile

Abstract

A semiconductor device and a method of fabricating the same suppress a substrate floating effect without causing lowering of a degree of integration. The semiconductor device has a Silicon-On-Insulator structure which includes a semiconductor layer formed on an insulator, and has at least one MOSFET element. The MOSFET element includes a source region; a drain region which is opposed to the source region; a body region disposed between the source and drain regions; a gate region positioned on or close to a surface of the body region, so as to form an electrically conducting channel in the body region; and an extracting region being in contact with both of the body region and the source region. The extracting region has a conductivity type which is the same as a conductivity type of the body region and has a concentration higher than that of the body region.

Claims

1. A semiconductor device having a Silicon-On-Insulator structure which includes a semiconductor layer formed on an insulator, and having at least one Metal-Oxide-Semiconductor-Field-Effect-Transistor (MOSFET) element, the MOSFET element comprising:

a source region;

a drain region which is opposed to said source region;

a body region disposed between said source region and said drain region;

a gate region positioned on or close to a surface of said body region, so as to form an electrically conducting channel in said body region;

an extracting region being in contact with both of said body region and said source region, said extracting region having a conductivity type which is the same as a conductivity type of said body region, and having an impurity concentration higher than that of said body region; and

a defect layer in which lattice defects are formed, said defect layer being formed in a neighborhood of said extracting region.

2. A semiconductor device according to claim 1, wherein said defect layer is in contact with both of said source region and said extracting region.

3. A semiconductor device according to claim 1, wherein said defect layer is a region of silicon ion implantation.

4. A semiconductor device according to claim 1, wherein said defect layer is a region of arsenic ion implantation.

5. A semiconductor device according to claim 1, further comprising an extension region in contact with said source region and formed above said extracting region, wherein the impurity concentration in said extracting region is higher than an impurity concentration in said extension region.

6. A semiconductor device according to claim 5, wherein the impurity concentration of said extraction region is in the range from about 1×

10¹⁹ cm⁺³ to about 1×

10²⁰ cm<sup>−

3</sup>.

7. A semiconductor device comprising:

a semiconductor layer on an insulator;

a source region in said semiconductor layer;

a drain region in said semiconductor layer, said drain region being opposed to said source region;

a body region of said semiconductor layer between said source region and said drain region;

a gate positioned on or close to a surface of said body region;

an extracting region in said semiconductor layer, in contact with said body region and said source region, said extracting region having a conductivity type which is the same as a conductivity type of said body region, and having an impurity concentration higher than an impurity concentration of said body region,

wherein said extracting region extends from said source region to directly under the gate; and

a defect layer disposed near said extracting region, said defect layer having lattice defects therein.

8. A semiconductor device according to claim 7, wherein said defect layer is a region of silicon or arsenic ion implantation.

9. A semiconductor device according to claim 7, wherein said defect layer is in contact with both of said source region and said extracting region.

10. A semiconductor device according to claim 7, further comprising an extension region in contact with said source region and formed above said extracting region, wherein the impurity concentration in said extracting region is higher than an impurity concentration in said extension region.

11. A semiconductor device according to claim 10, wherein the impurity concentration of said extraction region is in the range from about 1×

10¹⁹ cm<sup>−

3</sup> to about 1×

10²⁰ cm<sup>−

3</sup>.