Apparatus and methods for maskless pattern generation

• US 7,176,545 B2
• Filed: 01/27/2004
• Issued: 02/13/2007
• Est. Priority Date: 04/08/1992
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: ELM TECHNOLOGY CORPORATION
• Inventors: Leedy, Glenn J
• Primary Examiner(s): HO, TU TU V
• Application Number:
  US10/766,629
• Publication Number:
  US 20040192045A1
• Time in Patent Office: 1,113 Days
• Field of Search: 438/489, 438/377, 438/378, 438/351, 257/443
• US Class Current: 257/443
• CPC Class Codes: B81B 2203/0127 Diaphragms, i.e. structures separating two media that can control the passage from one medium to another; Membranes, i.e. diaphragms with filtering function
• CPC Class Codes: B81B 2207/07 Interconnects
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: B81C 2201/014 by depositing an etch stop layer, e.g. silicon nitride, silicon oxide, metal
• CPC Class Codes: B81C 2203/075 the electronic processing unit being integrated into an element of the micromechanical structure
• CPC Class Codes: G02F 1/13452 Conductors connecting driver circuitry and terminals of panels
• CPC Class Codes: G02F 1/136281 having a transmissive semiconductor substrate
• CPC Class Codes: G03F 7/70658 Electrical testing
• CPC Class Codes: G11C 29/006 at wafer scale level, i.e. wafer scale integration [WSI]
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/76289 Lateral isolation by air gap
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/538 the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates H05K takes precedence; manufacture or treatment H01L21/4846 ; mountings per se H01L23/12; materials H01L23/49866
• CPC Class Codes: H01L 23/5381 Crossover interconnections, e.g. bridge stepovers
• CPC Class Codes: H01L 23/5383 Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5386 Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 23/5387 : Flexible insulating substrates H01L23/5388 takes precedence
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/0102 : Calcium [Ca]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15165 : Monolayer substrate
• CPC Class Codes: H01L 2924/15312 : being a pin array, e.g. PGA
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: Y10S 438/949 : Energy beam treating radiation resist on semiconductor

Abstract

General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.

Claims

1. An apparatus for forming a patterned layer during manufacture of an integrated circuit, comprising:

an elastic integrated circuit;

a plurality of exposure elements;

means for selectively irradiating with at least one type of radiant energy portions of a surface of a layer by electronically controlling individually each of the exposure elements; and

at least one stress-controlled dielectric layer.

2. The apparatus of claim 1, wherein the at least one type of radiant energy is selected from the group consisting of optical, Deep Ultra Violet, X-ray, electron, proton, and particle beam.

3. The apparatus of claim 1, wherein the exposure elements are miniature sources of at least one of the following types of radiant energy:

X-ray, Deep Ultra Violet, and electron.

4. The apparatus of claim 1, wherein the exposure elements control passage of radiant energy from an external source.

5. The apparatus of claim 4, wherein the exposure elements control passage of radiant energy from an external source using at least one of the following mechanisms:

electromagnetic deflection, electrostatic deflection and mechanical shuttering.

6. The apparatus of claim 1, comprising means for separately focusing radiant energy emitted from each of multiple different exposure elements.

7. The apparatus of claim 1, comprising means for:

ceasing irradiating the surface;

shifting the exposure elements with respect to the surface; and

resuming irradiating the surface.

8. The apparatus of claim 1, wherein the stress of the at least one stress-controlled dielectric layer is less than about 8×

10⁸ dynes/cm².

9. The apparatus of claim 8, wherein the stress is tensile.

10. The apparatus of claim 1, wherein the stress of the at least one stress-controlled dielectric layer is 2 to 100 times less than the fracture strength of the at least one stress-controlled dielectric layer.

11. The apparatus of claim 10, wherein the stress is tensile.

12. The apparatus of claim 1, wherein the plurality of exposure elements includes at least one million elements.

13. The apparatus of claim 1, wherein the at least one stress-controlled dielectric layer is at least one of elastic and flexible.

14. The apparatus of claim 1, wherein the at least one stress-controlled dielectric layer is capable of forming at least one of a flexible membrane and a free standing membrane.

15. The apparatus of claim 1, wherein the at least one stress-controlled dielectric layer is selected from the group consisting of oxides of silicon, nitrides of silicon, silicon dioxide and silicon nitride.

16. The apparatus of claim 1, further comprising a plurality of interconnect conductors formed within the at least one stress-controlled dielectric layer.

17. The apparatus of claim 1, wherein the at least one stress-controlled dielectric layer is formed by at least one of Plasma Enhanced Chemical Vapor Deposition and multiple RF energy sources.

18. The apparatus of claim 1, wherein the at least one stress-controlled dielectric layer is formed at a temperature of about 400°

C.

19. The apparatus of claim 1, further comprising at least one elastic dielectric layer.

20. An apparatus for forming a patterned layer during manufacture of an integrated circuit, comprising:

an elastic integrated circuit;

a plurality of exposure elements;

means for selectively irradiating with at least one type of radiant energy portions of a surface of a layer by electronically controlling individually each of the exposure elements; and

at least one elastic dielectric layer, wherein the stress of the at least one elastic dielectric layer is less than about 8×

10⁸ dynes/cm².

21. The apparatus of claim 20, wherein the stress is tensile.

22. An apparatus for forming a patterned layer during manufacture of an integrated circuit, comprising:

an elastic integrated circuit;

a plurality of exposure elements; and

means for selectively irradiating with at least one type of radiant energy portions of a surface of a layer by electronically controlling individually each of the exposure elements, wherein said plurality of exposure elements are formed on a substrate, said apparatus further comprising a stress-controlled dielectric layer formed at least one of over and on the substrate.

23. The apparatus of claim 22, wherein the at least one type of radiant energy is selected from the group consisting of optical, Deep Ultra Violet, X-ray, electron, proton, and particle beam.

24. The apparatus of claim 22, wherein the exposure elements are miniature sources of at least one of the following types of radiant energy:

X-ray, Deep Ultra Violet, and electron.

25. The apparatus of claim 22, wherein the exposure elements control passage of radiant energy from an external source.

26. The apparatus of claim 25, wherein the exposure elements control passage of radiant energy from an external source using at least one of the following mechanisms:

electromagnetic deflection, electrostatic deflection and mechanical shuttering.

27. The apparatus of claim 22, comprising means for separately focusing radiant energy emitted from each of multiple different exposure elements.

28. The apparatus of claim 22, comprising means for:

ceasing irradiating the surface;

shifting the exposure elements with respect to the surface; and

resuming irradiating the surface.

29. The apparatus of claim 22, wherein the stress of the at least one stress-controlled dielectric layer is less than about 8×

10⁸ dynes/cm².

30. The apparatus of claim 29, wherein the stress is tensile.

31. The apparatus of claim 22, further comprising at least one elastic dielectric layer.

32. The apparatus of claim 31, wherein the stress of the at least one elastic dielectric layer is less than about 8×

10⁸ dynes/cm².

33. The apparatus of claim 32, wherein the stress is tensile.

34. The apparatus of claim 22, wherein the plurality of exposure elements includes at least one million elements.

35. The apparatus of claim 22, wherein the stress of the at least one stress-controlled dielectric layer is 2 to 100 times less than the fracture strength of the at least one stress-controlled dielectric layer.

36. The apparatus of claim 35, wherein the stress is tensile.

37. The apparatus of claim 22, wherein the at least one stress-controlled dielectric layer is at least one of elastic and flexible.

38. The apparatus of claim 22, wherein the at least one stress-controlled dielectric layer is capable of forming at least one of a flexible membrane and a free standing membrane.

39. The apparatus of claim 22, wherein the at least one stress-controlled dielectric layer is selected from the group consisting of oxides of silicon, nitrides of silicon, silicon dioxide and silicon nitride.

40. The apparatus of claim 22, further comprising a plurality of interconnect conductors formed within the at least one stress-controlled dielectric layer.

41. The apparatus of claim 22, wherein the at least one stress-controlled dielectric layer is formed by at least one of Plasma Enhanced Chemical Vapor Deposition and multiple RF energy sources.

42. The apparatus of claim 22, wherein the at least one stress-controlled dielectric layer is formed at a temperature of about 400°

C.