Semiconductor system-in-package

• US 7,176,556 B2
• Filed: 03/08/2002
• Issued: 02/13/2007
• Est. Priority Date: 10/26/2001
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Shioga, Takeshi, Taniguchi, Osamu, Omote, Koji, Yamagishi, Yasuo, Imanaka, Yoshihiko, Okamoto, Keishiro
• Primary Examiner(s): Owens; Douglas W.
• Assistant Examiner(s): Gebremariam; Samuel A
• Application Number:
  US10/092,525
• Publication Number:
  US 20030080400A1
• Time in Patent Office: 1,803 Days
• Field of Search: 257/503, 257/621, 257/528, 257/516, 257/532, 257/535, 257/724, 257/723, 257/774, 257/780, 257/507
• US Class Current: 257/621
• CPC Class Codes: H01L 21/4846 Leads on or in insulating or insulated substrates, e.g. metallisation H01L21/4821 takes precedence; metallisation of ceramics in general C04B41/51; printed circuits H05K3/00
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/16238 the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01046 Palladium [Pd]
• CPC Class Codes: H01L 2924/01077 Iridium [Ir]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A semiconductor apparatus comprises a support substrate having through holes filles with conductor adapted to a first pitch; a capacitor formed on or above said support substrate; a wiring layer formed on or above said support substrate, leading some of said through holes filles with conductor upwards through said capacitor, having branches, and having wires of a second pitch different from said first pitch; and plural semiconductor elements disposed on or above said wiring layer, having terminals adapted to the second pitch, and connected with said wiring layer via said terminals. A semiconductor apparatus, in which semiconductor elements having a narrow terminal pitch, a support having through wires at a wider pitch, and a capacitor are suitably electrically connected to realize the decoupling function with reduced inductance and large capacitance.

Claims

1. A semiconductor apparatus, comprising:

a support substrate made of a semiconductor substrate having only straight through holes filled with conductor in conformity with a first uniform pitch,

a capacitor formed on or above said support substrate comprising a lower electrode having a first wide area and a first cut-away portion, a dielectric film covering the first wide area, and an upper electrode having a second wide area and a second cut-away portion, the first and second wide areas facing via the dielectric film to establish a capacitance,

wiring layer formed on or above said support substrate, leading some of said straight through holes filled with conductor upwards via one of said wide areas and one of said cut-away portions of said capacitor,

said wiring layer having branches above said upper electrode to form wires of a second uniform pitch narrower than said first uniform pitch, and

plural semiconductor elements disposed on or above said wiring layer, having terminals in conformity with the second uniform pitch, and connected with said wiring layer via said terminals.

2. The semiconductor apparatus, according to claim 1, further comprising a circuit board having wiring of a first uniform pitch and connected to lower surfaces of said through holes filled with conductor.

3. The semiconductor apparatus, according to claim 2, wherein said support substrate is a Si substrate having through holes with an insulation film formed on the side walls of the holes, and said through holes filled with conductor are metallic conductors packed in said through holes.

4. The semiconductor apparatus, according to claim 3, wherein said through holes filled with conductor include a first signal wire;

said wiring layer contains a second signal wire for leading the first signal wire substantially vertically; and

said capacitor has electrodes with a vacancy around a region where said second signal wire is located.

5. The semiconductor apparatus, according to claim 4, wherein said capacitor has a capacitor dielectric layer made of an oxide containing at least one of Ba, Sr and Ti, and a pair of capacitor electrodes sandwiching the capacitor dielectric layer and containing at least partially one of Pt, Ir, Ru, Pd or any of their oxides.

6. The semiconductor apparatus, according to claim 1, wherein said support substrate is a Si substrate having through holes with an insulation film formed on the side walls of the holes, and said through holes filled with conductor are metallic conductors packed in said through holes.

7. The semiconductor apparatus, according to claim 6, wherein said insulation film is a silicon oxide film formed by thermal oxidation, and upper and lower surfaces of said silicon substrate are also covered with a silicon oxide film.

8. The semiconductor apparatus, according to claim 1, wherein said capacitor is a decoupling capacitor connected between power wires, and said wiring layer has branches between said decoupling capacitor and at least one of said semiconductor elements.

9. The semiconductor apparatus, according to claim 1, wherein said through holes filled with conductor include a first signal wire;

said wiring layer contains a second signal wire for leading the first signal wire substantially vertically; and

said capacitor has electrodes with a vacancy around a region where said second signal wire is located.

10. The semiconductor apparatus, according to claim 1, further comprising an insulation layer disposed on said support substrate, having a thermal expansion coefficient of 10 ppm/°

C. or less in the in-plane direction, and insulating said wiring layer and said capacitor.

11. The semiconductor apparatus, according to claim 1, wherein said capacitor has a capacitor dielectric layer made of an oxide containing at least one of Ba, Sr and Ti, and a pair of capacitor electrodes sandwiching the capacitor dielectric layer and containing at least partially one of Pt, Ir, Ru, Pd or any of their oxides.

12. The semiconductor apparatus, according to claim 1, wherein said wiring layer contains a wiring connecting said plural semiconductor elements with each other.

13. The semiconductor apparatus, according to claim 1, further comprising another circuit part connected with said wiring layer.