Semiconductor device

• US 7,176,577 B2
• Filed: 12/14/2004
• Issued: 02/13/2007
• Est. Priority Date: 06/11/1998
• Status: Expired due to Fees

• Current Assignee: LAPIS Semiconductor Co., Ltd. (ROHM Co., Ltd.)
• Original Assignee: OKI Electric Industry Company Limited
• Inventors: Harada, Yusuke
• Primary Examiner(s): Weiss; Howard
• Assistant Examiner(s): PIZARRO CRESPO, MARCOS D
• Application Number:
  US11/010,339
• Publication Number:
  US 20050098889A1
• Time in Patent Office: 791 Days
• Field of Search: 257382-385, 257750-767, 257/774, 257/915, 257/E23.145, 257/E23.161
• US Class Current: 257/774
• CPC Class Codes: H01L 21/76805 the opening being a via or contact hole penetrating the underlying conductor
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76847 the layer being positioned within the main fill metal
• CPC Class Codes: H01L 21/76852 the layer also covering the sidewalls of the conductive structure
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device is made up of a first insulating layer having a through hole; a first interconnection which comprises a first conductive layer, a first barrier layer, and a first main interconnection, and a second interconnection connected to one of the fist conductive layer and the first barrier layer. Accordingly, the semiconductor device can avoid a problem so that the Cu of the first main interconnection transfers from a portion connected to the second interconnection due to cause electromigration, the connected portion becomes a void, and the first interconnection is disconnected to the second interconnection.

Claims

1. A semiconductor device comprising:

a first insulating layer;

a first interconnection material formed in a first groove within the first insulating layer, the first interconnection material having a hole;

a second insulating layer formed on the first insulating layer;

a barrier layer formed in a second groove within the second insulating layer, the barrier layer extending from on the first interconnection material into the hole of the first interconnection material; and

a second interconnection material formed on a portion of the barrier layer that is on the first interconnection material, a part of the second interconnection material as a convex portion extends into the hole of the first interconnection material,

wherein the first interconnection material is electrically connected to the second interconnection material via the barrier layer by the convex portion inserted in the hole.

2. The semiconductor device of claim 1, wherein the first groove has a longitudinal direction corresponding to a flow of electrons.

3. The semiconductor device of claim 1, wherein the convex portion of the second interconnection material extends over an upper surface of the first interconnection material.

4. The semiconductor device of claim 1, wherein the second interconnection material is copper.

5. The semiconductor device of claim 1, wherein the first and second interconnection materials are copper.

6. The semiconductor device of claim 5, wherein the barrier layer comprises TiN.

7. The semiconductor device of claim 1, wherein the first interconnection material is copper.

8. The semiconductor device of claim 7, wherein the barrier layer comprises TiN.

9. The semiconductor device of claim 1, wherein the second groove has a conductive layer formed on inner surfaces thereof, the barrier layer formed on the conductive layer, and the second interconnection material formed on the barrier layer.

10. The semiconductor device of claim 9, wherein the barrier layer comprises TiN and the conductive layer comprises a barrier metal.

11. The semiconductor device of claim 10, wherein the second interconnection material is copper.

12. The semiconductor device of claim 9, wherein the first groove has a first conductive layer formed on inner surfaces thereof, a first barrier layer formed on the first conductive layer, and the first interconnection material formed on the first barrier layer.

13. The semiconductor device of claim 12, wherein the first barrier layer comprises TiN and the first conductive layer comprises one of a barrier metal and a silicide compound.

14. The semiconductor device of claim 13, wherein the first interconnection material is copper.