Display memory, driver circuit, display, and cellular information apparatus

• US 7,176,864 B2
• Filed: 09/27/2002
• Issued: 02/13/2007
• Est. Priority Date: 09/28/2001
• Status: Expired due to Fees

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Moriyama, Katsutoshi, Ayabe, Tomoya, Mizuta, Taishi
• Primary Examiner(s): Hjerpe; Richard
• Assistant Examiner(s): Shapiro; Leonid
• Application Number:
  US10/432,937
• Publication Number:
  US 20050099375A1
• Time in Patent Office: 1,600 Days
• Field of Search: 345/87, 345/89, 345/98, 345/100
• US Class Current: 345/87
• CPC Class Codes: G09G 2310/027 Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
• CPC Class Codes: G09G 2310/0297 Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 2330/026 Arrangements or methods related to booting a display
• CPC Class Codes: G09G 2330/027 Arrangements or methods related to powering off a display
• CPC Class Codes: G09G 2360/126 The frame memory having additional data ports, not inclusive of standard details of the output serial port of a VRAM
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 3/2003 Display of colours specific for liquid crystal displays G09G3/3607
• CPC Class Codes: G09G 3/3611 Control of matrices with row and column drivers
• CPC Class Codes: G09G 3/3685 Details of drivers for data electrodes
• CPC Class Codes: G09G 5/001 Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory
• CPC Class Codes: G09G 5/395 Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen G09G5/399 takes precedence

Abstract

A display memory able to reduce power consumption, able to generate graphics at a high speed, and not needing memory mapping, a driver circuit, a display using the driver circuit, and a portable information apparatus, wherein a CPU read circuit is connected to one bit line of a display memory 7, a display read circuit is connected to the other bit line, a write circuit is connected to both bit lines, the CPU read circuit and write circuit are assigned to the access from the CPU, the display read circuit is assigned to the display screen display, and further the access from the CPU and the reading to the display screen are assigned to different two level periods of a clock signal of the memory and independently controlled. Further, a drive power supply of the display memory is divided and a drive power supply voltage is supplied to the display memory for every memory cell or for every plurality of memory cells.

Claims

1. A display memory for storing pixel data to be supplied to pixels of a display, comprising:

at least one pair of bit lines;

at least one column of memory cells each having a first storage node and a second storage node able to hold states of a complementary first level and second level;

a first read circuit for reading the stored data of said first storage node output to one bit line of said pair of bit lines;

a second read circuit for reading the stored data of said second storage node output to the other bit line of said pair of bit lines;

a write circuit for outputting the data of said first level and second level to said first and second storage nodes of said memory cells to each the pair of bit lines and writing the data into said memory cells;

a controlling means for controlling the operation of said display memory;

a write port including at least one said write circuit;

a first read port including at least one said first read circuit; and

a second read port including at least one said second read circuit, wherein,

said first read port supplies the data stored in said memory cell to said display,

said second read port reads the data from said memory cell and outputs the same to said controlling means,

said write port writes the data from said controlling means into said memory cell,

said second read circuit inverts and outputs the level of the stored data of said second storage node output to said other bit line,

in a first level period of a clock signal of said display memory, said first read port performs a first access for outputting the data read via said first read circuit to said display, and

in a second level period of the clock signal of said display memory, said second read port and said write port perform a second access for outputting the data read via said second read circuit to said controlling means and inputting the write data to be written into said memory cell from said controlling means.

2. A display memory as set forth in claim 1, wherein:

said memory comprises a bit selecting means for selecting the memory cell into which the data is to be written, and

said write circuit outputs the data of said first level and second level at said first and second storage nodes of the memory cell selected by said bit selecting means to each of the pair of bit lines of the memory cell to be written.

3. A display memory as set forth in claim 1, wherein said memory comprises:

a drive use power supply voltage source for said display memory and

a switching device for selectively connecting a power supply voltage supply end of at least one memory cell and said drive use power supply voltage source.

4. A display memory as set forth in claim 1, wherein:

signal terminals for said first access are arrayed at one side part of said display memory, signal terminals for said second access are arrayed in the other side part different from that one side part, and

a first interface for said first access and a second interface for said second access are connected to said first access use signal terminals and said second access use signal terminals of said display memory while sandwiching said display memory therebetween.

5. A display memory as set forth in claim 4, wherein:

said first interface has a first line latch for storing one line'"'"'s worth of image data in a horizontal direction of pixels arrayed in said matrix,

said write port outputs said one line'"'"'s worth of data to the selected bit line via the first line latch, and

said second read port outputs said one line'"'"'s worth of data from said display memory to said controlling means.

6. A display memory as set forth in claim 4, wherein:

said second interface has a second line latch for storing one line'"'"'s worth of image data in the horizontal direction of pixels arrayed in a matrix, and

said first read port outputs said one line'"'"'s worth of data from said display memory to said display via the second line latch.

7. A display memory as set forth in claim 4, wherein,

in said display, a plurality of pixel cells are arrayed in a matrix,

in said display memory, a plurality of memory cells are arrayed in a matrix corresponding to the matrix array of said plurality of pixel cells,

in each memory cell, the pixel data for driving the corresponding pixel cell of the matrix of said display is stored by said write port, and

said first read port latches the image data in units of lines and supplies the same to the pixels of the corresponding line of said display.

8. A driver circuit for driving pixels arrayed in a matrix of a display by signals corresponding to image data stored in a display memory, wherein said display memory comprises:

at least one pair of bit lines;

at least one column of memory cells each having a first storage node and a second storage node able to hold states of a complementary first level and second level;

a first read circuit for reading the stored data of said first storage node output to one bit line of said pair of bit lines;

a second read circuit for reading the stored data of said second storage node output to the other bit line of said pair of bit lines;

a write circuit for outputting the data of said first level and second level to said first and second storage nodes of said memory cells to each the pair of bit lines and writing the data into said memory cells;

a controlling means for controlling the operation of said display memory;

a write port including at least one said write circuit;

a first read port including at least one said first read circuit; and

a second read port including at least one said second read circuit, wherein,

said first read port supplies the data stored in said memory cell to said display,

said second read port reads the data from said memory cell and outputs the same to said controlling means,

said write port writes the data from said controlling means into said memory cell,

said second read circuit inverts and outputs the level of the stored data of said second storage node output to said other bit line,

in a first level period of a clock signal of said display memory, said first read port performs a first access for outputting the data read via said first read circuit to said display, and

in a second level period of the clock signal of said display memory, said second read port and said write port perform a second access for outputting the data read via said second read circuit to said controlling means and inputting the write data to be written into said memory cell from said controlling means.

9. A driver circuit set forth in claim 8, wherein:

said display memory comprises a bit selecting means for receiving a write control signal and selecting the memory cell into which the data is to be written, and

said write circuit outputs the data of said first level and second level at said first and second storage nodes of the memory cell selected by said bit selecting means to each of the pair of bit lines of the memory cell to be written.

10. A driver circuit as set forth in claim 8, wherein said display memory comprises:

a drive use power supply voltage source for said display memory and

a switching device for selectively connecting a power supply voltage supply end of at least one memory cell and said drive use power supply voltage source.

11. A driver circuit as set forth in claim 8, wherein:

signal terminals for said first access are arrayed at one side part of said display memory, signal terminals for said second access are arrayed in the other side part different from that one side part, and

a first interface for said first access and a second interface for said second access are connected to said first access use signal terminals and said second access use signal terminals of said display memory while sandwiching said display memory therebetween.

12. A driver circuit as set forth in claim 11, wherein:

said first interface has a first line latch for storing one line'"'"'s worth of image data in a horizontal direction of pixels arrayed in said matrix,

said write port outputs said one line'"'"'s worth of data to the selected bit line via the first line latch, and

said second read port outputs said one line'"'"'s worth of data from said display memory to said controlling means.

13. A driver circuit as set forth in claim 11, wherein:

said first line latch stores for every pixel write control data for designating the pixel data to be written into said display memory in the pixel data latched in said first line latch, and

said write port writes the pixel data latched at said first line latch designated by the write control data into said display memory.

14. A driver circuit as set forth in claim 11, wherein,

in said display, a plurality of pixel cells are arrayed in a matrix,

in said display memory, a plurality of memory cells are arrayed in a matrix corresponding to the matrix array of said plurality of pixel cells,

in each memory cell of said display memory, the pixel data for driving the corresponding pixel cell of the matrix of said display is stored by said write port, and

said first read port latches the image data in units of lines and supplies the same to the pixels of the corresponding line of said display.

15. A driver circuit as set forth in claim 14, wherein each image data in the one line of said display'"'"'s worth of image data latched by said first line latch is stored in said display memory as image data for driving a corresponding pixel in the pixels of the corresponding line of said display.

16. A driver circuit as set forth in claim 11, wherein:

said second interface has a second line latch for storing one line'"'"'s worth of image data in the horizontal direction of pixels arrayed in a matrix, and

said first read port outputs said one line'"'"'s worth of data from said display memory to said display via the second line latch.

17. A driver circuit as set forth in claim 16, wherein a bit width of said second line latch is the same as a bit width of one line'"'"'s worth of image data in the horizontal direction of said pixels arrayed in a matrix.

18. A driver circuit as set forth in claim 16, wherein said second interface further comprises:

a selection circuit for sequentially selecting R, G, B data included in the image data held in said second line latch and converting said image data to time divided signals and

digital/analog converting means for converting digital signals to analog signals,

said selection circuit outputs the time divided signals obtained by time division of the R, G, B data included in said image data to said digital/analog converting means, and

said digital/analog converting means convert the time divided signals to the analog signals and supply the same to said display.

19. A driver circuit as set forth in claim 18, wherein said selection circuit selects the R, G, B data included in the pixel data held in said line latch asynchronously to the clock signal of said display memory and converts them to time divided signals.